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<feed xmlns="http://www.w3.org/2005/Atom"><title>Layman's Guide to Computing - Season 11</title><link href="https://ngjunsiang.github.io/laymansguide/" rel="alternate"></link><link href="https://ngjunsiang.github.io/laymansguide/feeds/season-11.atom.xml" rel="self"></link><id>https://ngjunsiang.github.io/laymansguide/</id><updated>2021-10-23T08:00:00+08:00</updated><entry><title>Issue 143: Implications (Part 2) – Future Goals</title><link href="https://ngjunsiang.github.io/laymansguide/issue143.html" rel="alternate"></link><published>2021-10-23T08:00:00+08:00</published><updated>2021-10-23T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-10-23:/laymansguide/issue143.html</id><summary type="html"></summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; Using the same hardware for both smartphones and laptops would make it much easier to write apps for both platforms. The closer they are in features, hardware, and software support, the easier things will be for&amp;nbsp;developers.&lt;/p&gt;
&lt;p&gt;So, let’s get some Likely-Asked-Questions (LAQs) out of the way in this last&amp;nbsp;issue.&lt;/p&gt;
&lt;h2&gt;If developing for a single chip makes things much easier for developers, can we just decide to develop everything for the M1 chip and somehow force Apple to share the chip&amp;nbsp;design?&lt;/h2&gt;
&lt;p&gt;You know as well as I do that the answer is no. Besides, Apple doesn’t care about the hardware needs of devices other than its own. You want other features they don’t care about? Too&amp;nbsp;bad.&lt;/p&gt;
&lt;h2&gt;So only Apple users get to enjoy unified&amp;nbsp;memory?&lt;/h2&gt;
&lt;p&gt;Yes, for now. We’ll need to wait a few years for other chipmakers to figure out their own hardware&amp;nbsp;implementations.&lt;/p&gt;
&lt;h2&gt;Who’s likely to achieve it&amp;nbsp;first?&lt;/h2&gt;
&lt;p&gt;This’ll have to be a company that designs its own CPUs and&amp;nbsp;GPUs.&lt;/p&gt;
&lt;p&gt;The incentives don’t align for Intel. Their main business has never relied on capable graphics, and they are much more concerned with saving the server market from &lt;span class="caps"&gt;ARM&lt;/span&gt;’s and &lt;span class="caps"&gt;AMD&lt;/span&gt;’s&amp;nbsp;encroachment.&lt;/p&gt;
&lt;p&gt;What about &lt;span class="caps"&gt;AMD&lt;/span&gt;? After all, they were one of the earliest companies to push for a similar idea: Heterogeneous System Architecture. And they achieved it to a lesser extent, with their Accelerated Processing Units (see &lt;a href="https://ngjunsiang.github.io/laymansguide/issue142.html"&gt;Issue 142&lt;/a&gt;); a fancy term for &lt;span class="caps"&gt;CPU&lt;/span&gt;+&lt;span class="caps"&gt;GPU&lt;/span&gt;).&lt;/p&gt;
&lt;p&gt;&lt;span class="caps"&gt;AMD&lt;/span&gt; has made this possible in software; that means as a programmer, you can command the &lt;span class="caps"&gt;CPU&lt;/span&gt; to store data at a memory address, pass that address to the &lt;span class="caps"&gt;GPU&lt;/span&gt;, and then get the &lt;span class="caps"&gt;GPU&lt;/span&gt; to retrieve data from that address. But in practice, benchmarks show that passing data this way falls short of the actual throughput that would be expected; possibly the hardware support is just not there yet, and not easy enough to&amp;nbsp;use.&lt;/p&gt;
&lt;p&gt;But the incentives line up quite well for &lt;span class="caps"&gt;AMD&lt;/span&gt;. If they achieve it, the performance of their APUs, their mid-range product, will see a significant boost. But they will need significant influence with developers to develop software development kits (SDKs) that developers can use to take advantage of unified memory, and that’s a big investment of&amp;nbsp;resources.&lt;/p&gt;
&lt;p&gt;Nvidia is putting a lot of effort into catching up on the &lt;span class="caps"&gt;CPU&lt;/span&gt; side of things, and they have been pushing lots of &lt;span class="caps"&gt;ARM&lt;/span&gt; chip designs to complement their strength in graphics cards. They have also recently bought &lt;span class="caps"&gt;ARM&lt;/span&gt;, so they also seem like a strong contender to implement unified memory. My gut sense is that it is not high on their priority list, as their primary business is still parallel computing and related applications, such as machine learning and scientific&amp;nbsp;computing.&lt;/p&gt;
&lt;p&gt;The work for this will have to be ongoing, of course, and likely started since 2015 or so; starting in 2021 is way too&amp;nbsp;late!&lt;/p&gt;
&lt;h2&gt;What does this mean for&amp;nbsp;Apple?&lt;/h2&gt;
&lt;p&gt;They are now almost fully in control of their own hardware and software. The main limitations where their control does not reach is their cloud computing (where iCloud happens), and the manufacturing (likely still &lt;span class="caps"&gt;TSMC&lt;/span&gt; in the near future). Their concerns now will be much more international than&amp;nbsp;before.&lt;/p&gt;
&lt;h2&gt;Should we expect to see unified memory on non-Apple&amp;nbsp;chips?&lt;/h2&gt;
&lt;p&gt;Yes, definitely, it’s something the industry has been working towards, just way too slowly &amp;#8230; and hopefully the M1’s existence will put some pressure on those development&amp;nbsp;timelines.&lt;/p&gt;
&lt;p&gt;I suspect the main cause of inertia is all the legacy software that still has to be supported. Because Intel and &lt;span class="caps"&gt;AMD&lt;/span&gt; have a lot of business riding on keeping compatibility with past hardware, they can&amp;#8217;t make sweeping changes across their entire range of products, unlike Apple. Every change that is made to an existing line of chips has to still keep it working when customers run their existing&amp;nbsp;software.&lt;/p&gt;
&lt;h2&gt;How does this affect&amp;nbsp;consumers?&lt;/h2&gt;
&lt;p&gt;Probably not much effect, beyond the gradual speed gains from generation to generation that we are already&amp;nbsp;seeing.&lt;/p&gt;
&lt;p&gt;The more significant effect is, I think, the miniaturisation of mobile systems. Already the mainboard for a laptop like the Macbook has shrunk to a narrow rectangle; most of the space for devices is now taken up by energy storage (i.e. batteries). The limiting factor now seems to be energy density: how many grams of batteries we will need per hour of laptop use. I suspect this is going to keep laptops more or less at the same size; the laptop is a mature form factor at this point and will gradually&amp;nbsp;age.&lt;/p&gt;
&lt;p&gt;What’s more exciting is when unified memory architectures can be miniaturised sufficiently for wearables. We are going to need that if we want augmented reality (&lt;span class="caps"&gt;AR&lt;/span&gt;) systems, e.g. graphics projected directly on a lens in front of our eyes, in a compact form factor. Many virtual reality (&lt;span class="caps"&gt;VR&lt;/span&gt;) and &lt;span class="caps"&gt;AR&lt;/span&gt; systems currently come in bulky designs that sit heavily on the body; there is much room for improvement&amp;nbsp;here.&lt;/p&gt;
&lt;h2&gt;Wrapping&amp;nbsp;up&lt;/h2&gt;
&lt;p&gt;This somehow ended up as a crash course in CPUs and GPUs, all in one season. I didn’t mean to carry out an industry analysis here, and this is definitely not a forecast to be relied on! It’s just a very interesting story to follow and I can’t help but think about what’s happening on multiple&amp;nbsp;levels.&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S12] Issue 144:&amp;nbsp;Programs-in-a-vat&lt;/p&gt;
&lt;p&gt;How does a program on the computer know if it is in a&amp;nbsp;simulation?&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;</content><category term="Season 11"></category></entry><entry><title>Issue 142: Implications (Part 1) - Software</title><link href="https://ngjunsiang.github.io/laymansguide/issue142.html" rel="alternate"></link><published>2021-10-16T08:00:00+08:00</published><updated>2021-10-16T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-10-16:/laymansguide/issue142.html</id><summary type="html">&lt;p&gt;Using the same hardware for both smartphones and laptops would make it much easier to write apps for both platforms. The closer they are in features, hardware, and software support, the easier things will be for&amp;nbsp;developers.&lt;/p&gt;</summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; The Apple A14 and Apple M1 are essentially the same chip architecture: they use almost the same building blocks, just with different numbers of them. On top of that, the Apple M1 implements unified memory, allowing the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; (and other SoC components) to share the same system memory, greatly facilitating intra-chip&amp;nbsp;communication.&lt;/p&gt;
&lt;p&gt;So, before 2020: smartphones are smartphones, laptops are laptops. They use different types of CPUs with different architectures (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue141.html"&gt;Issue 141&lt;/a&gt;)) and even different instruction sets (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue053.html"&gt;Issue 53&lt;/a&gt;)). Never the twain shall&amp;nbsp;meet.&lt;/p&gt;
&lt;p&gt;After 2020: It turns out that smartphone chips can be upgraded and used in laptops, while remaining essentially the same architecture? Its power consumption dial can be turned down to almost zero but also turned all the way&amp;nbsp;up?&lt;/p&gt;
&lt;p&gt;That opens up the possibility that smartphones and laptops can run on the same hardware, and there’s nothing technically stopping apps compiled (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue054.html"&gt;Issue 54&lt;/a&gt;)) for that instruction set to run on both!&lt;sup id="fnref:1"&gt;&lt;a class="footnote-ref" href="#fn:1"&gt;1&lt;/a&gt;&lt;/sup&gt;&lt;/p&gt;
&lt;p&gt;Hmm, where has something like this happened&amp;nbsp;before?&lt;/p&gt;
&lt;h2&gt;The big console&amp;nbsp;alignment&lt;/h2&gt;
&lt;p&gt;Sometime in mid-2013, Microsoft announced the Xbox One (henceforth &lt;span class="caps"&gt;XB1&lt;/span&gt;), the successor to the Xbox 360. The 360 ran on a PowerPC &lt;span class="caps"&gt;CPU&lt;/span&gt; made by &lt;span class="caps"&gt;IBM&lt;/span&gt;—different from smartphone chips that used the &lt;span class="caps"&gt;ARM&lt;/span&gt; instruction set, and also different from laptops that use the x86 instruction set.&lt;sup id="fnref:2"&gt;&lt;a class="footnote-ref" href="#fn:2"&gt;2&lt;/a&gt;&lt;/sup&gt;&lt;/p&gt;
&lt;p&gt;The Xbox One, on the other hand, uses a &lt;span class="caps"&gt;CPU&lt;/span&gt;+&lt;span class="caps"&gt;GPU&lt;/span&gt; made by &lt;span class="caps"&gt;AMD&lt;/span&gt;&lt;sup id="fnref:3"&gt;&lt;a class="footnote-ref" href="#fn:3"&gt;3&lt;/a&gt;&lt;/sup&gt;, following the x86 instruction&amp;nbsp;set.&lt;/p&gt;
&lt;p&gt;The Xbox One essentially uses a custom laptop&amp;nbsp;chip!&lt;/p&gt;
&lt;p&gt;This &lt;em&gt;was&lt;/em&gt; interesting news because earlier that year, in Feb 2013, Sony had announced the PlayStation 4 (&lt;span class="caps"&gt;PS4&lt;/span&gt;), which was &amp;#8230; also running on an &lt;span class="caps"&gt;AMD&lt;/span&gt; &lt;span class="caps"&gt;CPU&lt;/span&gt;+&lt;span class="caps"&gt;GPU&lt;/span&gt;! The previous iteration, the PlayStation 3 (&lt;span class="caps"&gt;PS3&lt;/span&gt;), was running on an interesting custom architecture that used PowerPC cores and a completely original &lt;span class="caps"&gt;GPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;At this point it would be oh-so-tempting, for a tech nerd, to descend into point-by-point comparisons of the hardware specifications of both consoles. We will fortunately not be doing&amp;nbsp;that.&lt;/p&gt;
&lt;p&gt;What’s more important is what this meant for the video&amp;nbsp;games.&lt;/p&gt;
&lt;h2&gt;Alignment in game&amp;nbsp;development&lt;/h2&gt;
&lt;p&gt;If you wanted to write a game for the Xbox 360, you had to learn its &lt;span class="caps"&gt;API&lt;/span&gt;: which functions to call to make it do what you want, how to store data into its storage, and so on. It’s a lot of time and effort to look at your options and figure out the limitations, and how to work around them to achieve what you want in your&amp;nbsp;game.&lt;/p&gt;
&lt;p&gt;And if you wanted to make the same game for the &lt;span class="caps"&gt;PS3&lt;/span&gt;, you now had to learn a completely different &lt;span class="caps"&gt;API&lt;/span&gt;, running on hardware with completely different limitations, and figuring out completely different approaches to achieve the same end. While the game might feel the same, the time and effort is almost as much as what it would take for a new&amp;nbsp;game!&lt;/p&gt;
&lt;p&gt;The &lt;span class="caps"&gt;XB1&lt;/span&gt; and &lt;span class="caps"&gt;PS4&lt;/span&gt;, on the other hand, are much more similar. They both use &lt;span class="caps"&gt;AMD&lt;/span&gt; &lt;span class="caps"&gt;CPU&lt;/span&gt;+GPUs with similar architecture. While Microsoft and Sony may add their own features on top of the chips and the software, the &lt;span class="caps"&gt;API&lt;/span&gt; is ultimately guided by hardware decisions. If you made a game for &lt;span class="caps"&gt;XB1&lt;/span&gt; and wanted to port it to &lt;span class="caps"&gt;PS4&lt;/span&gt;, the effort of learning a new &lt;span class="caps"&gt;API&lt;/span&gt; is greatly&amp;nbsp;lessened.&lt;/p&gt;
&lt;h2&gt;The gulf between smartphones and&amp;nbsp;laptops&lt;/h2&gt;
&lt;p&gt;Back to smartphones vs laptops. Running on two different types of chips, using different architectures and instruction&amp;nbsp;sets.&lt;/p&gt;
&lt;p&gt;We have seen some forays from one into the other: Intel’s doomed Medfield chip was an attempt to bring the x86 architecture to smartphones, while Google has been trying to get &lt;span class="caps"&gt;ARM&lt;/span&gt; chips into Chromebooks, with limited but increasing&amp;nbsp;success.&lt;/p&gt;
&lt;p&gt;But now that we have an iPhone 12 using the A14 chip, a Macbook using the M1 chip, and we know that the A14 and M1 are essentially the same architecture and the same instruction set … it does suggest that the challenges of making software for both devices now primarily exist on the software side. The gulf of hardware incompatibility has been&amp;nbsp;closed.&lt;/p&gt;
&lt;h2&gt;Feature&amp;nbsp;alignment&lt;/h2&gt;
&lt;p&gt;The M1 chip is capable of power standby (i.e. screen off with the &lt;span class="caps"&gt;CPU&lt;/span&gt; in a low-power state), in a way that most laptop chips aren’t. This is a key feature for smartphone software and operating systems, and the M1 paves the way for laptop chip-makers to introduce this feature into their processors as&amp;nbsp;well.&lt;/p&gt;
&lt;p&gt;And the M1, being living proof that unified memory is possible, would also likely push existing companies to speed up development towards that&amp;nbsp;goal.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Issue summary:&lt;/strong&gt; Using the same hardware for both smartphones and laptops would make it much easier to write apps for both platforms. The closer they are in features, hardware, and software support, the easier things will be for&amp;nbsp;developers.&lt;/p&gt;
&lt;p&gt;I was looking for a way to sneak in the &lt;span class="caps"&gt;XB1&lt;/span&gt;-and-&lt;span class="caps"&gt;PS4&lt;/span&gt; story, and I think I found just the right place for it. It really does excite me to think that one day a developer could write software for a smartphone, and it would work on laptops with minimal modification, and vice-versa. And perhaps a decade from now, we’d be scratching our heads why we even had to choose between the&amp;nbsp;two!&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S10] Issue 143: Implications (Part 2) – Future&amp;nbsp;Goals&lt;/p&gt;
&lt;p&gt;So what’s next? Is unified memory the holy grail for hardware, and is there any further room for improvement? I’ll share some thoughts in the next&amp;nbsp;issue.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;
&lt;div class="footnote"&gt;
&lt;hr /&gt;
&lt;ol&gt;
&lt;li id="fn:1"&gt;
&lt;p&gt;Nothing, that is, besides all the software workarounds that will need to be written &amp;#8230;&amp;#160;&lt;a class="footnote-backref" href="#fnref:1" title="Jump back to footnote 1 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;li id="fn:2"&gt;
&lt;p&gt;In an interesting narrative twist, PowerPC was the architecture that Macbooks used before Apple switched them to Intel processors. And now Xbox did the same thing.&amp;#160;&lt;a class="footnote-backref" href="#fnref:2" title="Jump back to footnote 2 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;li id="fn:3"&gt;
&lt;p&gt;&lt;span class="caps"&gt;AMD&lt;/span&gt; calls it an Accelerated Processing Unit (&lt;span class="caps"&gt;APU&lt;/span&gt;). Doesn’t matter for us.&amp;#160;&lt;a class="footnote-backref" href="#fnref:3" title="Jump back to footnote 3 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;/ol&gt;
&lt;/div&gt;</content><category term="Season 11"></category></entry><entry><title>Issue 141: The Apple A14 and M1</title><link href="https://ngjunsiang.github.io/laymansguide/issue141.html" rel="alternate"></link><published>2021-10-09T08:00:00+08:00</published><updated>2021-10-09T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-10-09:/laymansguide/issue141.html</id><summary type="html">&lt;p&gt;The Apple A14 and Apple M1 are essentially the same chip architecture: they use almost the same building blocks, just with different numbers of them. On top of that, the Apple M1 implements unified memory, allowing the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; (and other SoC components) to share the same system memory, greatly facilitating intra-chip&amp;nbsp;communication.&lt;/p&gt;</summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; Shared memory is easier to implement when a company has control over the designs of both &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;So, to&amp;nbsp;recap:&lt;/p&gt;
&lt;p&gt;Most companies design either CPUs or GPUs, but seldom are well-positioned&lt;sup id="fnref:1"&gt;&lt;a class="footnote-ref" href="#fn:1"&gt;1&lt;/a&gt;&lt;/sup&gt; to be excellent in&amp;nbsp;both.&lt;/p&gt;
&lt;p&gt;Among the companies that design both CPUs and GPUs, almost none of them&lt;sup id="fnref:2"&gt;&lt;a class="footnote-ref" href="#fn:2"&gt;2&lt;/a&gt;&lt;/sup&gt; make CPUs for both mobile (smartphones + tablets) as well as laptops (including low- to mid-range desktops).&lt;sup id="fnref:3"&gt;&lt;a class="footnote-ref" href="#fn:3"&gt;3&lt;/a&gt;&lt;/sup&gt;&lt;/p&gt;
&lt;p&gt;Which leaves Apple in the (current) position of being the only chip company with a design for both mobile as well as&amp;nbsp;laptop.&lt;/p&gt;
&lt;h2&gt;The difficulties of power&amp;nbsp;scaling&lt;/h2&gt;
&lt;p&gt;It’s not that other companies have not attempted&amp;nbsp;this.&lt;/p&gt;
&lt;p&gt;They have tried to scale down laptop chips to achieve smartphone-like power consumption, but found that laptop chips can’t power down the way smartphone chips can, and require more circuitry to achieve&amp;nbsp;that.&lt;/p&gt;
&lt;p&gt;They have also tried to scale smartphone chips up to achieve laptop-like computational capacity, but found that simply pushing more electrical power doesn’t help all that much. Beyond a certain frequency limit, you simply need more bandwidth and more units, and designing a chip that easily accommodates more units like this just requires a very different&amp;nbsp;design.&lt;/p&gt;
&lt;p&gt;It seems that designing a chip that can go from 4W all the way to 65W (and possibly higher) requires intentional engineering, not simply modifying an existing smartphone/laptop chip design or bolting on/removing&amp;nbsp;features.&lt;/p&gt;
&lt;h2&gt;The Apple A14 vs the Apple M1:&amp;nbsp;similarities&lt;/h2&gt;
&lt;p&gt;Apple has managed to do just this with the Apple A14 and M1. They are, at heart, the same chip design! (In processor parlance, we say they have the same &lt;strong&gt;chip architecture&lt;/strong&gt;.)&lt;/p&gt;
&lt;p&gt;Let’s&amp;nbsp;see:&lt;/p&gt;
&lt;p&gt;&lt;img alt="Apple A14 hardware overview" src="https://ngjunsiang.github.io/laymansguide/issue141_01.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;The Apple A14’s key hardware.&lt;br /&gt;Source: &lt;a href="https://www.electrony.net/350867/%D8%A7%D9%84%D9%85%D8%B9%D8%A7%D9%84%D8%AC-apple-a14-bionic-%D9%82%D8%AF-%D9%8A%D9%88%D9%81%D8%B1-%D8%A3%D8%AF%D8%A7%D8%A1%D9%8B-%D9%85%D9%85%D8%A7%D8%AB%D9%84%D8%A7%D9%8B-%D9%84%D8%A3%D8%AF%D8%A7/apple-a14/"&gt;Apparently an online Arabic image gallery site&lt;/a&gt; (I have no idea why this picture is so hard to&amp;nbsp;find!)&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;&lt;img alt="Apple M1 hardware overview" src="https://ngjunsiang.github.io/laymansguide/issue141_02.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;The Apple M1’s key hardware.&lt;br /&gt;Source: &lt;a href="https://www.techbuzzpro.com/apple-introduces-m1-5nm-octa-core-soc-for-the-mac.html"&gt;TechBuzzPro&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;We can also compare these features via&amp;nbsp;Wikipedia:&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Apple&amp;nbsp;A14&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;6-core &lt;span class="caps"&gt;CPU&lt;/span&gt; (4 low-power&lt;sup id="fnref:4"&gt;&lt;a class="footnote-ref" href="#fn:4"&gt;4&lt;/a&gt;&lt;/sup&gt; cores “Icestorm”, &lt;strong&gt;2&lt;/strong&gt; high-performance “Firestorm”&amp;nbsp;cores)&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;4&lt;/strong&gt;-core &lt;span class="caps"&gt;GPU&lt;/span&gt;&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;8&lt;/strong&gt;-core &lt;span class="caps"&gt;NPU&lt;/span&gt;&lt;/li&gt;
&lt;li&gt;&lt;span class="caps"&gt;4GB&lt;/span&gt; memory (iPhone 12) / &lt;span class="caps"&gt;6GB&lt;/span&gt; memory (iPhone 12&amp;nbsp;Pro)&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;&lt;strong&gt;Apple&amp;nbsp;M1&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;8-core &lt;span class="caps"&gt;CPU&lt;/span&gt; (4 low-power&lt;sup id="fnref2:4"&gt;&lt;a class="footnote-ref" href="#fn:4"&gt;4&lt;/a&gt;&lt;/sup&gt; cores “Icestorm”, &lt;strong&gt;4&lt;/strong&gt; high-performance “Firestorm”&amp;nbsp;cores)&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;8&lt;/strong&gt;-core &lt;span class="caps"&gt;GPU&lt;/span&gt;&lt;/li&gt;
&lt;li&gt;&lt;strong&gt;16&lt;/strong&gt;-core &lt;span class="caps"&gt;NPU&lt;/span&gt;&lt;/li&gt;
&lt;li&gt;&lt;span class="caps"&gt;8GB&lt;/span&gt; memory / &lt;span class="caps"&gt;16GB&lt;/span&gt;&amp;nbsp;memory&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;Notice that at heart, they are using the same building blocks: &lt;del&gt;low-power&lt;/del&gt; high-efficiency cores, high-performance cores, &lt;span class="caps"&gt;GPU&lt;/span&gt; cores, and &lt;span class="caps"&gt;NPU&lt;/span&gt; cores (I suspect these are &lt;span class="caps"&gt;GPU&lt;/span&gt;-like cores but optimised for machine learning, i.e. they probably power Siri and other parts of the &lt;span class="caps"&gt;OS&lt;/span&gt; which lean on &lt;span class="caps"&gt;AI&lt;/span&gt; features); the A14 and M1 just has different numbers of&amp;nbsp;them.&lt;/p&gt;
&lt;p&gt;So one really amazing thing about the Apple M1 is that it is actually a boosted Apple A14: almost double the&amp;nbsp;hardware!&lt;/p&gt;
&lt;p&gt;It’s like when Magnemites join together and evolve into a Magneton&amp;nbsp;…&lt;/p&gt;
&lt;h2&gt;The Apple A14 vs the Apple M1:&amp;nbsp;differences&lt;/h2&gt;
&lt;p&gt;What’s different between the A14 and M1, besides the number of key chips? Apple isn’t forthcoming with the details, but we can guess about minor details like the image processor (for camera imaging), storage controller (the M1 can use high-power solid-state disks (SSDs) which the A14&amp;nbsp;can’t).&lt;/p&gt;
&lt;p&gt;The major difference announced between the A14 and M1 launch is that the M1 has unified&amp;nbsp;memory.&lt;/p&gt;
&lt;h2&gt;Unified memory vs &lt;span class="caps"&gt;CPU&lt;/span&gt;–&lt;span class="caps"&gt;GPU&lt;/span&gt;&amp;nbsp;transfers&lt;/h2&gt;
&lt;p&gt;Back in &lt;a href="https://ngjunsiang.github.io/laymansguide/issue139.html"&gt;Issue 139&lt;/a&gt;), I mentioned that unified memory needs really high bandwidth to support access by the SoC&amp;nbsp;components.&lt;/p&gt;
&lt;p&gt;Today, laptop processors use an interface called PCIe to connect CPUs to GPUs. PCIe has a bandwidth of up to 16 &lt;span class="caps"&gt;GB&lt;/span&gt;/s&lt;sup id="fnref:5"&gt;&lt;a class="footnote-ref" href="#fn:5"&gt;5&lt;/a&gt;&lt;/sup&gt;.&lt;/p&gt;
&lt;p&gt;The M1’s unified memory has a bandwidth of up to &lt;em&gt;58 &lt;span class="caps"&gt;GB&lt;/span&gt;/s&lt;/em&gt; reading from memory, and &lt;em&gt;36 &lt;span class="caps"&gt;GB&lt;/span&gt;/s&lt;/em&gt; writing to memory. Definitely an&amp;nbsp;improvement.&lt;/p&gt;
&lt;h2&gt;Unified memory: what’s yours is also&amp;nbsp;mine&lt;/h2&gt;
&lt;p&gt;The &lt;span class="caps"&gt;8GB&lt;/span&gt;/&lt;span class="caps"&gt;16GB&lt;/span&gt; of system memory is used by both &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt;. It is not partitioned at boot; both the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; (and other parts of the SoC, such as the &lt;span class="caps"&gt;NPU&lt;/span&gt;) have &lt;em&gt;full access to all system memory&lt;/em&gt;.&lt;/p&gt;
&lt;p&gt;This greatly simplifies intra-chip communication, as all subchips in the SoC can request access to memory! The &lt;span class="caps"&gt;GPU&lt;/span&gt; no longer needs to keep its own (power-guzzling) memory. This reduces the motherboard space that is needed, lowers power consumption, and decreases latency for data transfer between &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue139.html"&gt;Issue 139&lt;/a&gt;)): a triple-compounding&amp;nbsp;win.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Issue summary:&lt;/strong&gt; The Apple A14 and Apple M1 are essentially the same chip architecture: they use almost the same building blocks, just with different numbers of them. On top of that, the Apple M1 implements unified memory, allowing the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; (and other SoC components) to share the same system memory, greatly facilitating intra-chip&amp;nbsp;communication.&lt;/p&gt;
&lt;p&gt;Some implications of the Apple A14–Apple M1 familial connection: the Apple M1 is truly capable of smartphone-like standby, a feature that Intel’s and &lt;span class="caps"&gt;AMD&lt;/span&gt;’s laptop chips have been striving for but not quite&amp;nbsp;achieved.&lt;/p&gt;
&lt;p&gt;It’s a lot to detail here, so instead I will do so—in a separate&amp;nbsp;issue.&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S10] Issue 142: Implications (Part 1) -&amp;nbsp;Software&lt;/p&gt;
&lt;p&gt;Besides the reported fact that the M1 is really very fast (and yes I will spend a little time explaining just how fast), what else does this herald for expectations in the software on devices? Coming up next issue&amp;nbsp;:)&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;
&lt;div class="footnote"&gt;
&lt;hr /&gt;
&lt;ol&gt;
&lt;li id="fn:1"&gt;
&lt;p&gt;Companies that achieve both &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; excellence generally have business incentives that align with that goal (as opposed to, say, making low-power or cheap processors)&amp;#160;&lt;a class="footnote-backref" href="#fnref:1" title="Jump back to footnote 1 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;li id="fn:2"&gt;
&lt;p&gt;Intel had a short-lived but ultimately doomed attempt at a smartphone chip (it was named Medfield).&amp;#160;&lt;a class="footnote-backref" href="#fnref:2" title="Jump back to footnote 2 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;li id="fn:3"&gt;
&lt;p&gt;I‘m going to ignore servers here because I can! And because they’re not really relevant to a discussion on low-power consumer chips.&amp;#160;&lt;a class="footnote-backref" href="#fnref:3" title="Jump back to footnote 3 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;li id="fn:4"&gt;
&lt;p&gt;These are the same ones labelled “high-efficiency”, which is marketing speak for “designed to use very little power”&amp;#160;&lt;a class="footnote-backref" href="#fnref:4" title="Jump back to footnote 4 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;a class="footnote-backref" href="#fnref2:4" title="Jump back to footnote 4 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;li id="fn:5"&gt;
&lt;p&gt;Bandwidth of 16 &lt;span class="caps"&gt;GB&lt;/span&gt;/s is for PICe 3.0; PCIe 4.0 will support up to 32 &lt;span class="caps"&gt;GB&lt;/span&gt;/s, but graphics cards won’t use that much bandwidth to communicate with the &lt;span class="caps"&gt;CPU&lt;/span&gt;.&amp;#160;&lt;a class="footnote-backref" href="#fnref:5" title="Jump back to footnote 5 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;/ol&gt;
&lt;/div&gt;</content><category term="Season 11"></category></entry><entry><title>Issue 140: The shared memory dream</title><link href="https://ngjunsiang.github.io/laymansguide/issue140.html" rel="alternate"></link><published>2021-10-02T08:00:00+08:00</published><updated>2021-10-02T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-10-02:/laymansguide/issue140.html</id><summary type="html">&lt;p&gt;Shared memory is easier to implement when a company has control over the designs of both &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt;.&lt;/p&gt;</summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; Around 2015, the high-performance computer industry quickly realised that this would be much more efficient if the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; could &lt;em&gt;share the same memory&lt;/em&gt;. This idea was labelled heterogeneous systems architecture (&lt;span class="caps"&gt;HSA&lt;/span&gt;).&lt;/p&gt;
&lt;p&gt;Let’s rewind a bit further from last issue. That was in&amp;nbsp;2015.&lt;/p&gt;
&lt;p&gt;Circa 2009, changes were happening on the desktop motherboard, as the memory controller hub (&lt;span class="caps"&gt;MCH&lt;/span&gt;) came on-board the &lt;span class="caps"&gt;CPU&lt;/span&gt; to reduce latency when communicating with memory (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue134.html"&gt;Issues 134&lt;/a&gt;)–&lt;a href="https://ngjunsiang.github.io/laymansguide/issue135.html"&gt;135&lt;/a&gt;)). But the memory chips themselves remained on the motherboard, and this was the case even in 2018, in Apple’s Macbook Air (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue136.html"&gt;Issue 136&lt;/a&gt;)).&lt;/p&gt;
&lt;h2&gt;Bringing memory&amp;nbsp;on-board&lt;/h2&gt;
&lt;p&gt;Smartphones can’t afford to do that; every bit of mainboard space is precious! The Apple A-series processors have been gradually moving more and more memory into the &lt;span class="caps"&gt;CPU&lt;/span&gt;, where it enjoys lower latency communicating with the &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;In 2013, Apple released the iPhone 5S, using the Apple A7 SoC. This was Apple’s first 64-bit SoC (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue055.html"&gt;Issue 55&lt;/a&gt;)), and by this point Apple had managed to bring &lt;span class="caps"&gt;1GB&lt;/span&gt; of memory onto the SoC package. By 2018, With the Apple A12 SoC, the on-board memory had increased up to &lt;span class="caps"&gt;4GB&lt;/span&gt; on high-end iPhone X&amp;nbsp;models.&lt;/p&gt;
&lt;p&gt;So in 2015, the high-performance folks (working with workstations and servers) were dreaming of the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; sharing memory, while from 2013, in smartphones, the &lt;span class="caps"&gt;CPU&lt;/span&gt;, &lt;span class="caps"&gt;GPU&lt;/span&gt;, and system memory were already cohabiting in the same chip package! &lt;span class="caps"&gt;CPU&lt;/span&gt;, &lt;span class="caps"&gt;GPU&lt;/span&gt;, and memory all living in the same space … how does this&amp;nbsp;work?&lt;/p&gt;
&lt;h2&gt;Memory: yours or&amp;nbsp;mine?&lt;/h2&gt;
&lt;p&gt;Remember this&amp;nbsp;diagram?&lt;/p&gt;
&lt;p&gt;&lt;img alt="Chipset diagram of ATX systems for Intel Core (i-Series)" src="https://ngjunsiang.github.io/laymansguide/issue134_02.gif" /&gt;&lt;br /&gt;
&lt;em&gt;An Intel Core i-series &lt;span class="caps"&gt;ATX&lt;/span&gt; system chipset diagram.&lt;br /&gt;The &lt;span class="caps"&gt;MCH&lt;/span&gt; is merged into the &lt;span class="caps"&gt;CPU&lt;/span&gt;, but still a discrete unit.&lt;br /&gt;&lt;span class="caps"&gt;DDR&lt;/span&gt; refers to computer memory, while &lt;span class="caps"&gt;GDDR&lt;/span&gt; refers to graphics card memory (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue123.html"&gt;Issue123&lt;/a&gt;))&lt;br /&gt;Source: &lt;a href="https://arstechnica.com/gadgets/2009/09/intel-launches-all-new-pc-architecture-with-core-i5i7-cpus/"&gt;Ars&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;Apple is pretty tight-lipped about the technical details of its products, but if the industry standard is anything to go by, the &lt;span class="caps"&gt;GPU&lt;/span&gt; will usually have its own memory, separate from the &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;After all, CPUs and GPUs don’t do the same work, or even work the same way (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue123.html"&gt;Issue 123&lt;/a&gt;)). They use different memory, they use memory differently, they store data differently, and if they accidentally overwrote each other’s data … well, your device would just&amp;nbsp;crash.&lt;/p&gt;
&lt;p&gt;So … that on-board memory, whose is it? &lt;span class="caps"&gt;CPU&lt;/span&gt;’s, or &lt;span class="caps"&gt;GPU&lt;/span&gt;’s?&lt;/p&gt;
&lt;h2&gt;Successful sharing looks like&amp;nbsp;&amp;#8230;&lt;/h2&gt;
&lt;p&gt;One thing that makes it difficult to share memory is that the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; have to “speak the same language”; they need a common shared understanding of the workflow involved in passing data through shared&amp;nbsp;memory.&lt;/p&gt;
&lt;p&gt;This is easier to develop when a single company has control over both &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; designs. This is not always the case; many smartphones have &lt;span class="caps"&gt;CPU&lt;/span&gt; designs from one company and &lt;span class="caps"&gt;GPU&lt;/span&gt; designs from&amp;nbsp;another!&lt;/p&gt;
&lt;p&gt;For instance, the Apple A-series processors initially used GPUs from a graphics company called Imagination Technologies, designed by their PowerVR division. With a &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; from different teams, working in different ways, shared memory is not likely to happen&lt;sup id="fnref:1"&gt;&lt;a class="footnote-ref" href="#fn:1"&gt;1&lt;/a&gt;&lt;/sup&gt;.&lt;/p&gt;
&lt;p&gt;But in the A10 SoC, released in 2016, Apple had subtly started to replace parts of the &lt;span class="caps"&gt;GPU&lt;/span&gt; with their own in-house designs. The A10 would be the last in the line of the “Fusion” SoC&amp;nbsp;series.&lt;/p&gt;
&lt;p&gt;When the A11 SoC was released in late 2017—first in the “Bionic” series of SoCs—PowerVR’s &lt;span class="caps"&gt;GPU&lt;/span&gt; had been replaced by Apple’s own design&lt;sup id="fnref:2"&gt;&lt;a class="footnote-ref" href="#fn:2"&gt;2&lt;/a&gt;&lt;/sup&gt;.&lt;/p&gt;
&lt;p&gt;Apple is finally in the position of working towards shared memory with their Bionic-series SoCs, with the A14 being the fourth “Bionic”&amp;nbsp;SoC.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Issue summary:&lt;/strong&gt; Shared memory is easier to implement when a company has control over the designs of both &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;The story which began in &lt;a href="https://ngjunsiang.github.io/laymansguide/issue138.html"&gt;Issue 138&lt;/a&gt;) is coming to a close soon! Next issue, the curtain falls, the A14 and M1 are released, and Apple (probably) pulls the chip industry in a new direction&amp;nbsp;again.&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S10] Issue 141: The Apple A14 and&amp;nbsp;M1&lt;/p&gt;
&lt;p&gt;And finally I can geek out over the A14 and M1 😎 don&amp;#8217;t worry, I’ll keep it&amp;nbsp;on-topic.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;
&lt;div class="footnote"&gt;
&lt;hr /&gt;
&lt;ol&gt;
&lt;li id="fn:1"&gt;
&lt;p&gt;What about other companies that had control over the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; designs? Such as &lt;span class="caps"&gt;AMD&lt;/span&gt;, Samsung, Qualcomm, &amp;#8230;? It’s a long story, and not really suitable for a layman newsletter. Sorry.&amp;#160;&lt;a class="footnote-backref" href="#fnref:1" title="Jump back to footnote 1 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;li id="fn:2"&gt;
&lt;p&gt;The design is technically Apple’s, but they had been learning from many generations of working with PowerVR’s &lt;span class="caps"&gt;GPU&lt;/span&gt;, so the early initial designs are very likely heavily influenced by it.&amp;#160;&lt;a class="footnote-backref" href="#fnref:2" title="Jump back to footnote 2 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;/ol&gt;
&lt;/div&gt;</content><category term="Season 11"></category><category term="memory"></category></entry><entry><title>Issue 139: What’s before this line is mine, what’s after this line is yours</title><link href="https://ngjunsiang.github.io/laymansguide/issue139.html" rel="alternate"></link><published>2021-09-25T08:00:00+08:00</published><updated>2021-09-25T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-09-25:/laymansguide/issue139.html</id><summary type="html">&lt;p&gt;Around 2015, the high-performance computer industry quickly realised that this would be much more efficient if the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; could &lt;em&gt;share the same memory&lt;/em&gt;.&lt;/p&gt;</summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; A system-on-chip (SoC) combines the core functionality of a system—processing, graphics, memory, and control—into a single chip&amp;nbsp;package.&lt;/p&gt;
&lt;p&gt;I am eager to dig into the meat of the A14 and M1! But first I must set up a&amp;nbsp;story.&lt;/p&gt;
&lt;h2&gt;The hUMA&amp;nbsp;race&lt;/h2&gt;
&lt;p&gt;Circa 2015 (actually even a couple of years before that), the industry suddenly seemed to wake up and realise that graphics cards could do a lot more than just play video games. The nature of how they work (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue121.html"&gt;Issue 121&lt;/a&gt;) &lt;span class="amp"&gt;&amp;amp;&lt;/span&gt; &lt;a href="https://ngjunsiang.github.io/laymansguide/issue122.html"&gt;122&lt;/a&gt;)) makes them very amenable to solving problems in scientific computing, particularly in simulations, which use up computational resources by the petaflop, and energy by the&amp;nbsp;megawatt.&lt;/p&gt;
&lt;p&gt;In a nutshell, the problem the industry now faces is&amp;nbsp;this:&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;The &lt;span class="caps"&gt;GPU&lt;/span&gt; is massively powerful &amp;#8230; at doing a small subset of things. You can solve scientific equations but can’t run a computer with &lt;em&gt;only&lt;/em&gt; a &lt;span class="caps"&gt;GPU&lt;/span&gt;.&lt;/li&gt;
&lt;li&gt;The &lt;span class="caps"&gt;CPU&lt;/span&gt; is nimble, and much more suited for everyday tasks, like starting up a computer and connecting to multiple peripherals, and basically creating a useable digital environment for&amp;nbsp;humans.&lt;/li&gt;
&lt;li&gt;It thus makes the best sense to use the &lt;span class="caps"&gt;CPU&lt;/span&gt; to set up the heavy-lifting for the &lt;span class="caps"&gt;GPU&lt;/span&gt;, and have the &lt;span class="caps"&gt;GPU&lt;/span&gt; return the results after&amp;nbsp;computation.&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;Remember this diagram from &lt;a href="https://ngjunsiang.github.io/laymansguide/issue134.html"&gt;Issue 134&lt;/a&gt;)?&lt;/p&gt;
&lt;p&gt;&lt;img alt="Chipset diagram of ATX systems for Intel Core (i-Series)" src="https://ngjunsiang.github.io/laymansguide/issue134_02.gif" /&gt;&lt;/p&gt;
&lt;p&gt;Think about how information would flow&amp;nbsp;here:&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;The &lt;span class="caps"&gt;CPU&lt;/span&gt; requests data from the hard disks, which get put &lt;em&gt;into system memory&lt;/em&gt; (&lt;span class="caps"&gt;DDR&lt;/span&gt;; left-most&amp;nbsp;side).&lt;/li&gt;
&lt;li&gt;It carries out some pre-processing on that data to set up the task for the &lt;span class="caps"&gt;GPU&lt;/span&gt;, reading from memory, and storing the results back in&amp;nbsp;memory.&lt;/li&gt;
&lt;li&gt;The data is &lt;strong&gt;copied&lt;/strong&gt; &lt;em&gt;from system memory&lt;/em&gt; to the &lt;span class="caps"&gt;GPU&lt;/span&gt;, which stores that data &lt;em&gt;in &lt;span class="caps"&gt;GPU&lt;/span&gt; memory&lt;/em&gt; (&lt;span class="caps"&gt;GDDR&lt;/span&gt;; right-most&amp;nbsp;side).&lt;/li&gt;
&lt;li&gt;The &lt;span class="caps"&gt;GPU&lt;/span&gt; carries out the task, storing the results &lt;em&gt;in &lt;span class="caps"&gt;GPU&lt;/span&gt; memory&lt;/em&gt;.&lt;/li&gt;
&lt;li&gt;The &lt;span class="caps"&gt;CPU&lt;/span&gt; requests the data from &lt;span class="caps"&gt;GPU&lt;/span&gt; memory, &lt;strong&gt;copying&lt;/strong&gt; it back &lt;em&gt;into system memory&lt;/em&gt;.&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;Are you seeing lots of wasted effort there? I bolded it in case you missed it. So much copying of&amp;nbsp;information!&lt;/p&gt;
&lt;p&gt;The high-performance computer industry quickly realised that it could be much more efficient if the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; could &lt;em&gt;share the same memory&lt;/em&gt;.&lt;/p&gt;
&lt;p&gt;The information flow in this hypothetical memory-sharing system would be simplified to&amp;nbsp;this:&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;The &lt;span class="caps"&gt;CPU&lt;/span&gt; requests data from the hard disks, which get put &lt;em&gt;into shared memory&lt;/em&gt;.&lt;/li&gt;
&lt;li&gt;The &lt;span class="caps"&gt;CPU&lt;/span&gt; pre-processes the data, storing it back into shared&amp;nbsp;memory.&lt;/li&gt;
&lt;li&gt;The &lt;span class="caps"&gt;CPU&lt;/span&gt; sends &lt;em&gt;the location&lt;/em&gt; of the data to the &lt;span class="caps"&gt;GPU&lt;/span&gt;, which then reads &lt;em&gt;from shared memory&lt;/em&gt; and carries out the task, storing the results back &lt;em&gt;into shared&amp;nbsp;memory&lt;/em&gt;&lt;/li&gt;
&lt;li&gt;The &lt;span class="caps"&gt;CPU&lt;/span&gt; retrieves the results directly &lt;em&gt;from shared memory&lt;/em&gt;.&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;We save time, bandwidth, and resources without having to copy data between &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt;, twice! The only drawback is that with so many components (&lt;span class="caps"&gt;CPU&lt;/span&gt;, &lt;span class="caps"&gt;GPU&lt;/span&gt;, and others) accessing memory at the same time, you are going to need memory with really high&amp;nbsp;bandwidth.&lt;/p&gt;
&lt;p&gt;The industry gave this dream a name. They called it &lt;a href="https://en.wikipedia.org/wiki/Heterogeneous_System_Architecture"&gt;heterogeneous system architecture (&lt;span class="caps"&gt;HSA&lt;/span&gt;)&lt;/a&gt;, using a heterogeneous unified memory architecture (hUMA) i.e. shared&amp;nbsp;memory.&lt;/p&gt;
&lt;p&gt;&lt;img alt="Unified memory diagram from Nvidia" src="https://ngjunsiang.github.io/laymansguide/issue139_01.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;Nvidia’s heterogeneous unified memory architecture (&lt;span class="caps"&gt;HUMA&lt;/span&gt;) dream&lt;br /&gt;Source: &lt;a href="https://wccftech.com/intel-amd-nvidia-future-industry-hsa/2/"&gt;WCCFtech&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;It turns out that this is a pretty difficult task—consider the amount of bandwidth needed to support &lt;span class="caps"&gt;CPU&lt;/span&gt; &lt;em&gt;and&lt;/em&gt; &lt;span class="caps"&gt;GPU&lt;/span&gt; access. Today no product from any company (besides Apple) fully implements this in its SoCs (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue138.html"&gt;Issue 138&lt;/a&gt;))&amp;nbsp;yet.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Issue summary:&lt;/strong&gt; Around 2015, the high-performance computer industry quickly realised that this would be much more efficient if the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; could &lt;em&gt;share the same memory&lt;/em&gt;.&lt;/p&gt;
&lt;p&gt;I should stop here with this issue, and summarise the struggles of these companies in the next issue. They will make Apple’s success with the A14 &lt;span class="amp"&gt;&amp;amp;&lt;/span&gt; M1 a much more compelling read&amp;nbsp;:)&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S10] Issue 140: The shared memory&amp;nbsp;dream&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;</content><category term="Season 11"></category><category term="memory"></category></entry><entry><title>Issue 138: System-on-Chip (SoC)</title><link href="https://ngjunsiang.github.io/laymansguide/issue138.html" rel="alternate"></link><published>2021-09-18T08:00:00+08:00</published><updated>2021-09-18T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-09-18:/laymansguide/issue138.html</id><summary type="html">&lt;p&gt;A system-on-chip (SoC) combines the core functionality of a system—processing, graphics, memory, and control—into a single chip&amp;nbsp;package.&lt;/p&gt;</summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; The M1 goes one step further: not only does it make do with fewer chips, it does so with passive&amp;nbsp;cooling.&lt;/p&gt;
&lt;p&gt;In &lt;a href="https://ngjunsiang.github.io/laymansguide/issue136.html"&gt;Issue 136&lt;/a&gt;), I showed the miniaturisation of the Macbook mainboard through a series of pictures. While the laptop has remained the same size mostly (apart from getting slimmer), that is not the case with its components. The bigger components, like memory and storage, changed from being separate discrete parts to being another component soldered directly to the&amp;nbsp;mainboard.&lt;/p&gt;
&lt;p&gt;But that only gets us so far; even in the M1 Macbook Air, the mainboard is still almost the entire length of a phone. There’s got to be something&amp;nbsp;else.&lt;/p&gt;
&lt;p&gt;Today, let’s see how the iPhone has&amp;nbsp;evolved.&lt;/p&gt;
&lt;h2&gt;What’s in a smartphone:&amp;nbsp;2008&lt;/h2&gt;
&lt;p&gt;Rewind to 2008: one year after the first-generation iPhone was launched, the iPhone 3G was released. These early smartphones let us see every little chip that was required to run a&amp;nbsp;smartphone:&lt;/p&gt;
&lt;p&gt;&lt;img alt="iPhone 3G mainboard, with parts labelled" src="https://ngjunsiang.github.io/laymansguide/issue138_01.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;iPhone 3G mainboard, with parts labelled&lt;br /&gt;There are lots of small, auxiliary processors around the &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/Teardown/iPhone+3G+Teardown/600"&gt;iFixit&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;In spirit and form, the early smartphones were a lot like the early desktop mainboards (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue132.html"&gt;Issue 132&lt;/a&gt;)): lots of chips performing highly specific&amp;nbsp;functions.&lt;/p&gt;
&lt;p&gt;After all, a smartphone has no need (or space) for a peripheral controller hub (&lt;span class="caps"&gt;PCH&lt;/span&gt;) (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue134.html"&gt;Issue 134&lt;/a&gt;)) when it does not have add-on peripherals, and no need for a memory controller hub (&lt;span class="caps"&gt;MCH&lt;/span&gt;) when it can put the memory directly on the same chip as the &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;At this point, Apple was still using a &lt;span class="caps"&gt;CPU&lt;/span&gt; based on a design by &lt;span class="caps"&gt;ARM&lt;/span&gt;, and manufactured by Samsung. 2 years later, Apple had its own in-house processor: the Apple A4, their own&amp;nbsp;design.&lt;/p&gt;
&lt;h2&gt;What’s in a smartphone:&amp;nbsp;2010&lt;/h2&gt;
&lt;p&gt;This time, Apple had switched to an internal layout distinctly different from the iPhone 3G, and the basic layout (mainboard beside battery) would become a pattern for subsequent iPhone generations: battery taking up almost half the space, charging and audio circuitry at the bottom near the charging port, camera and antennas near the top, and everything else beside the&amp;nbsp;battery.&lt;/p&gt;
&lt;p&gt;&lt;img alt="iPhone 4 and iPhone 12 Pro" src="https://ngjunsiang.github.io/laymansguide/issue138_02.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;iPhone 4 on the left, iPhone 12 Pro on the right&lt;br /&gt;The basic layout of the iPhone has been preserved over a decade.&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/Teardown/iPhone+4+Teardown/3130"&gt;iFixit&lt;/a&gt; and &lt;a href="https://www.ifixit.com/Teardown/iPhone+12+and+12+Pro+Teardown/137669"&gt;iFixit&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;What’s the difference between this layout and the 3G? Let’s have a look at the iPhone 4’s&amp;nbsp;mainboard:&lt;/p&gt;
&lt;p&gt;&lt;img alt="iPhone 4 mainboard" src="https://ngjunsiang.github.io/laymansguide/issue138_03.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;iPhone 4 mainboard. I got lazy with the labelling because, well, there’s nothing to label!&lt;br /&gt;The &lt;span class="caps"&gt;CPU&lt;/span&gt; is the huge chip labelled “A4”, and there’s memory and the 3G chip on the back.&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/Teardown/iPhone+4+Teardown/3130"&gt;iFixit&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;Similar to the transition from &lt;span class="caps"&gt;AT&lt;/span&gt; to &lt;span class="caps"&gt;ATX&lt;/span&gt; motherboards (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue132.html"&gt;Issue 132&lt;/a&gt;) and &lt;a href="https://ngjunsiang.github.io/laymansguide/issue134.html"&gt;134&lt;/a&gt;)), the iPhone underwent a great miniaturisation—in a single&amp;nbsp;generation!&lt;/p&gt;
&lt;h2&gt;System-on-Chip&lt;/h2&gt;
&lt;p&gt;What happened to all those separate chips? Most of them got moved &lt;em&gt;onboard&lt;/em&gt;, into the A4 chip, or other auxiliary chips. The great consolidating brought all their functionality under one&amp;nbsp;roof.&lt;/p&gt;
&lt;p&gt;The A4 chip&amp;nbsp;carries:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;CPU&lt;/span&gt;&lt;sup id="fnref:1"&gt;&lt;a class="footnote-ref" href="#fn:1"&gt;1&lt;/a&gt;&lt;/sup&gt;&lt;/li&gt;
&lt;li&gt;&lt;span class="caps"&gt;GPU&lt;/span&gt;&lt;/li&gt;
&lt;li&gt;&lt;span class="caps"&gt;MCH&lt;/span&gt;&lt;/li&gt;
&lt;li&gt;&lt;span class="caps"&gt;PCH&lt;/span&gt;&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;This chip is responsible&amp;nbsp;for:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;performing&amp;nbsp;calculations&lt;/li&gt;
&lt;li&gt;rendering graphics (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue123.html"&gt;Issue 123&lt;/a&gt;))&lt;/li&gt;
&lt;li&gt;managing the flow of information between &lt;span class="caps"&gt;CPU&lt;/span&gt;, &lt;span class="caps"&gt;GPU&lt;/span&gt;, and memory (previously the job of the &lt;span class="caps"&gt;MCH&lt;/span&gt;)&lt;/li&gt;
&lt;li&gt;managing the flow of information between storage, network, and the &lt;span class="caps"&gt;MCH&lt;/span&gt; (previously the job of the &lt;span class="caps"&gt;PCH&lt;/span&gt;)&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;It is literally an entire system on a chip: a &lt;strong&gt;system-on-chip&lt;/strong&gt;&amp;nbsp;(SoC)!&lt;/p&gt;
&lt;p&gt;More and more functionality would gradually be migrated into the SoC itself, with fewer auxiliary chips required: sensors, gyroscopes, image processors for the camera, etc. More educational perhaps would be to look at what’s &lt;em&gt;not&lt;/em&gt; included in the SoC, particularly by the time we get to the the iPhone 12’s SoC, called the&amp;nbsp;A14.&lt;/p&gt;
&lt;p&gt;Not on the A14&amp;nbsp;SoC:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;solid state disk (only part of it is in the&amp;nbsp;SoC)&lt;/li&gt;
&lt;li&gt;power&amp;nbsp;management&lt;/li&gt;
&lt;li&gt;4G &lt;span class="amp"&gt;&amp;amp;&lt;/span&gt;&amp;nbsp;5G&lt;/li&gt;
&lt;li&gt;audio&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;The above functionality is highly specialised, especially in modern&lt;sup id="fnref:2"&gt;&lt;a class="footnote-ref" href="#fn:2"&gt;2&lt;/a&gt;&lt;/sup&gt; smartphones. It manages the remaining parts of the phone: camera &lt;span class="amp"&gt;&amp;amp;&lt;/span&gt; mic/speakers, wifi &lt;span class="amp"&gt;&amp;amp;&lt;/span&gt; bluetooth, and telecommunications (4G/5G). Telecommunications in particular require a lot of power and would have contributed to unnecessary heating in the small &lt;span class="caps"&gt;CPU&lt;/span&gt;&amp;nbsp;package.&lt;/p&gt;
&lt;p&gt;And this is how we shrink a laptop mainboard even&amp;nbsp;further.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Issue summary:&lt;/strong&gt; A system-on-chip (SoC) combines the core functionality of a system—processing, graphics, memory, and control—into a single chip&amp;nbsp;package.&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;The M1’s design shares a lot more in common with the A14 on the iPhone and iPad than it does with the laptop CPUs that came before it. I want to go into a bit more detail about this in the next issue, so that it’s easier to see just how different it is from a typical&amp;nbsp;laptop.&lt;/p&gt;
&lt;p&gt;First question: what exactly does “unified memory” mean? Why is Apple making it such a big&amp;nbsp;deal?&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S10] Issue 139: What’s before this line is mine, what’s after this line is&amp;nbsp;yours&lt;/p&gt;
&lt;p&gt;Next issue, we look at a trend that started being reported on in 2015: the high-performance computing industry realised that the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;GPU&lt;/span&gt; need to have much more integrated memory&amp;nbsp;sharing.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;
&lt;div class="footnote"&gt;
&lt;hr /&gt;
&lt;ol&gt;
&lt;li id="fn:1"&gt;
&lt;p&gt;The &lt;span class="caps"&gt;CPU&lt;/span&gt; carries (some) onboard memory for itself, but the main bulk of memory is still on the mainboard.&amp;#160;&lt;a class="footnote-backref" href="#fnref:1" title="Jump back to footnote 1 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;li id="fn:2"&gt;
&lt;p&gt;I know it’s strange to differentiate older vs newer smartphones when the technology is only 1.5 decades old. But the evolution of smartphone designs over the course has been significant enough that yes, I am going to make this distinction :)&amp;#160;&lt;a class="footnote-backref" href="#fnref:2" title="Jump back to footnote 2 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;/ol&gt;
&lt;/div&gt;</content><category term="Season 11"></category></entry><entry><title>Issue 137: The M1 Macbook Air</title><link href="https://ngjunsiang.github.io/laymansguide/issue137.html" rel="alternate"></link><published>2021-09-11T08:00:00+08:00</published><updated>2021-09-11T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-09-11:/laymansguide/issue137.html</id><summary type="html">&lt;p&gt;The M1 goes one step further: not only does it make do with fewer chips, it does so with passive&amp;nbsp;cooling!&lt;/p&gt;</summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; Slim laptops have been undergoing a gradual transition: more and more of their chips are no longer available as a replaceable card, but instead soldered directly to the mainboard. Since 2017/2018, most slim laptops pretty much have &lt;span class="caps"&gt;CPU&lt;/span&gt;, memory, storage, and network chips all soldered directly to the&amp;nbsp;mainboard.&lt;/p&gt;
&lt;p&gt;Let’s get to it: Intel vs M1 Macbook&amp;nbsp;Air!&lt;/p&gt;
&lt;h2&gt;The 2020 Macbook Air: passing the&amp;nbsp;torch&lt;/h2&gt;
&lt;p&gt;Here’s the Macbook Air in 2020. There was one in early 2020 using an Intel Core &lt;span class="caps"&gt;CPU&lt;/span&gt;, and one in late 2020 using the Apple M1 &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;&lt;img alt="Macbook Air in early 2020 (left), vs late 2020 (right)" src="https://ngjunsiang.github.io/laymansguide/issue137_01.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;Macbook Air, early-2020 (Intel, left) vs late-2020 (M1, right)&lt;br /&gt;&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/News/46884/m1-macbook-teardowns-something-old-something-new"&gt;iFixit&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;They look almost identical, but some parts are noticeably different … can you spot the&amp;nbsp;differences?&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;The cooling fan (upper left) is there in the early 2020 (Intel) model, but gone in the late 2020 (M1)&amp;nbsp;model.&lt;/li&gt;
&lt;li&gt;Besides the &lt;span class="caps"&gt;CPU&lt;/span&gt; (upper centre in both models, under a heatsink), the Intel model has a mysterious-looking chip (upper right, covered in black&amp;nbsp;shrouding)&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;You may have spotted other differences in the hardware, but since this issue is focused on the mainboard and &lt;span class="caps"&gt;CPU&lt;/span&gt;, let’s zoom in on those. Let’s have a closer look at their&amp;nbsp;mainboards:&lt;/p&gt;
&lt;p&gt;&lt;img alt="2020 Intel Macbook Air mainboard, front(left) vs back (right)" src="https://ngjunsiang.github.io/laymansguide/issue137_04.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;2020 Intel Macbook Air mainboard, front and back&lt;br /&gt;The Intel &lt;span class="caps"&gt;CPU&lt;/span&gt; unfortunately sits under the huge heatsink, shown with its 4 securing screws&lt;br /&gt;Memory and solid state disk are on separate chips (most likely on the back)&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/Store/Mac/MacBook-Air-13-Inch-Early-2020-1-1-GHz-Core-i3-Logic-Board-with-Paired-Touch-ID-Sensor/IF188-152?o=1"&gt;iFixit&amp;nbsp;Store&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;&lt;img alt="2020 M1 Macbook Air mainboard, front (left) vs back (right)" src="https://ngjunsiang.github.io/laymansguide/issue137_02.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;2020 M1 Macbook Air mainboard, front and back&lt;br /&gt;There are fewer big chips, but the single biggest chip there is &lt;/em&gt;much&lt;em&gt; bigger, and Apple-branded&lt;br /&gt;Memory is integrated into the &lt;span class="caps"&gt;CPU&lt;/span&gt;, but the solid state disk sits on a separate pair of chips&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/News/46884/m1-macbook-teardowns-something-old-something-new"&gt;iFixit&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;h2&gt;The M1 Macbook Air: all&amp;nbsp;aboard&lt;/h2&gt;
&lt;p&gt;Overall, it looks like the M1 has “swallowed” a number of chips. Compared to the 2020 Intel model, the M1 has brought on-board computer memory (the two black chips on the M1), and Apple’s T2 chip (the back shrouded chip on the 2020 Intel Macbook Air). These are major components for computer&amp;nbsp;operation.&lt;/p&gt;
&lt;p&gt;So not only does the M1 incorporate more components, it does so while drawing less power—the lack of a cooling fan implies it is passively cooled. From &lt;a href="https://ngjunsiang.github.io/laymansguide/issue129.html"&gt;Issue 129&lt;/a&gt;), this suggests the M1 Macbook Air also uses less power (8–12W) for its tasks. And reviews for the Macbook M1 Air suggest it is not being thermally throttled except under the heaviest of&amp;nbsp;loads.&lt;/p&gt;
&lt;p&gt;How did Apple manage to design a processor like&amp;nbsp;this?&lt;/p&gt;
&lt;h2&gt;The Apple M1: evolved from a smartphone&amp;nbsp;chip&lt;/h2&gt;
&lt;p&gt;To get into that story, I’ll have to go even more mobile, and look at smartphone CPUs. After all, the Apple M1 actually evolved from the Apple A-series CPUs for their iPhone and iPad. That starts next&amp;nbsp;issue.&lt;/p&gt;
&lt;h2&gt;What about other Intel Core laptops running&amp;nbsp;Windows?&lt;/h2&gt;
&lt;p&gt;They are largely undergoing the same transition, just more slowly. This is the Microsoft Surface Laptop in&amp;nbsp;2017:&lt;/p&gt;
&lt;p&gt;&lt;img alt="Microsoft Surface Laptop (2017) mainboard" src="https://ngjunsiang.github.io/laymansguide/issue137_03.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;Microsoft Surface Laptop mainboard&lt;br /&gt;&lt;span class="caps"&gt;CPU&lt;/span&gt;(red), memory (orange), solid state disk (yellow), and network card (green) are all soldered on. (Outlined in cyan are the display control chips)&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/Teardown/Microsoft+Surface+Laptop+Teardown/92915"&gt;iFixit&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;Larger-sized laptops that can afford the space may still have solid state storage on a separate&amp;nbsp;card.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Issue summary:&lt;/strong&gt; The M1 goes one step further: not only does it make do with fewer chips, it does so with passive&amp;nbsp;cooling!&lt;/p&gt;
&lt;p&gt;The last issue simply went on too long, especially with all the images, so I figured this issue would stand better as a Core-vs-M1 comparison, instead of being the tail of an evolution-of-Air issue. So it’s&amp;nbsp;short.&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S10] Issue 138: System-on-Chip&amp;nbsp;(SoC)&lt;/p&gt;
&lt;p&gt;If smartphones are even smaller than laptops, how do they do it? Laptops seem to have exhausted all the tricks, and those boards still look pretty&amp;nbsp;big.&lt;/p&gt;
&lt;p&gt;Next issue, I’ll talk about the next step in the evolution of shrinking&amp;nbsp;mainboards.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;</content><category term="Season 11"></category></entry><entry><title>Issue 136: The mobile workstation – laptops</title><link href="https://ngjunsiang.github.io/laymansguide/issue136.html" rel="alternate"></link><published>2021-09-04T08:00:00+08:00</published><updated>2021-09-04T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-09-04:/laymansguide/issue136.html</id><summary type="html">&lt;p&gt;Slim laptops have been undergoing a gradual transition: more and more of their chips are no longer available as a replaceable card, but instead soldered directly to the mainboard. Since 2017/2018, most slim laptops pretty much have &lt;span class="caps"&gt;CPU&lt;/span&gt;, memory, storage, and network chips all soldered directly to the&amp;nbsp;mainboard.&lt;/p&gt;</summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; A modern &lt;span class="caps"&gt;CPU&lt;/span&gt; is manufactured through a process called photolithography, by which the &lt;span class="caps"&gt;CPU&lt;/span&gt; components are etched onto the silicon substrate by successive layers of chemicals, masking, and laser exposure. When the &lt;span class="caps"&gt;CPU&lt;/span&gt; components could be made small enough, the &lt;span class="caps"&gt;MCH&lt;/span&gt; and &lt;span class="caps"&gt;CPU&lt;/span&gt; were designed onto the same chip, and this is the design used by the Intel Core i7&amp;nbsp;(1st-gen).&lt;/p&gt;
&lt;p&gt;In the last 4 issues, I walked through the general evolution of desktop computers. Let’s go more mobile, and look at laptops. How does something as big as a desktop shrink down to the size of a laptop? And what are the tradeoffs&amp;nbsp;involved?&lt;/p&gt;
&lt;p&gt;I addressed the power part of the formula in &lt;a href="https://ngjunsiang.github.io/laymansguide/issue130.html"&gt;Issue 130&lt;/a&gt;), on power limits; laptops are slimmer in part because part of them—the &lt;span class="caps"&gt;AC&lt;/span&gt; adapter—lies outside the&amp;nbsp;system.&lt;/p&gt;
&lt;p&gt;Let’s look at the rest of&amp;nbsp;it.&lt;/p&gt;
&lt;h2&gt;Laptops use slimmer&amp;nbsp;components&lt;/h2&gt;
&lt;p&gt;Laptops use slimmer memory than&amp;nbsp;desktops:&lt;/p&gt;
&lt;p&gt;&lt;img alt="Desktop memory vs Laptop memory" src="https://ngjunsiang.github.io/laymansguide/issue136_01.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;Desktop memory (&lt;span class="caps"&gt;DIMM&lt;/span&gt;) vs laptop memory (&lt;span class="caps"&gt;SODIMM&lt;/span&gt;)&lt;br /&gt;Source: &lt;a href="https://www.quora.com/What-type-of-memory-module-is-used-in-a-desktop-and-laptop-computer"&gt;Quora&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;On a desktop mainboard, desktop memory sticks out perpendicularly from the mainboard, all the better to cram memory sticks together and maximise the use of&amp;nbsp;space.&lt;/p&gt;
&lt;p&gt;On a laptop mainboard, laptop memory sticks lie parallel to the mainboard, to reduce the mainboard height and allow a slim laptop&amp;nbsp;profile.&lt;/p&gt;
&lt;p&gt;As far as I know &amp;#8230; there aren’t any other significant differences to highlight (besides size). Unless you’re overclocking, just get the kind of memory your computer/laptop needs. These days, small-form-factor desktops use laptop memory (&lt;span class="caps"&gt;SODIMM&lt;/span&gt;) as&amp;nbsp;well!&lt;/p&gt;
&lt;p&gt;Laptops use slimmer hard drives compared to desktops as&amp;nbsp;well:&lt;/p&gt;
&lt;p&gt;&lt;img alt="Desktop hard drive vs Laptop hard drive" src="https://ngjunsiang.github.io/laymansguide/issue136_02.png" /&gt;&lt;br /&gt;
&lt;em&gt;Desktop hard drive (3.5″) vs Laptop hard drive (2.5″)&lt;br /&gt;Source: &lt;a href="https://www.m2wificards.com/2-5-vs-3-5-hdd/"&gt;M2WifiCards&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;Desktop hard drives are larger, use larger platters (3.5″ diameter), and hence draw more power (at both 12V and 5V voltages). Laptop hard drives are smaller, use smaller platters (2.5″ diameter), and draw less power (at 5V voltage only). This is why smaller external hard drives, which use laptop hard drives, can be powered over &lt;span class="caps"&gt;USB&lt;/span&gt;, but larger external hard drives, which use desktop hard drives, need an external &lt;span class="caps"&gt;AC&lt;/span&gt;&amp;nbsp;adapter.&lt;/p&gt;
&lt;p&gt;These days, laptops have mostly made the transition to solid state disks, and you are much less likely to see hard drives in&amp;nbsp;laptops.&lt;/p&gt;
&lt;h2&gt;The slim laptop in 2010: Macbook&amp;nbsp;Air&lt;/h2&gt;
&lt;p&gt;Let’s examine how a characteristic slim laptop, the Macbook Air, has changed in the past 10&amp;nbsp;years.&lt;/p&gt;
&lt;p&gt;In 2010, the Macbook Air had its solid state disk and wifi network card on separate (replaceable) cards. But the &lt;span class="caps"&gt;CPU&lt;/span&gt;, &lt;span class="caps"&gt;GPU&lt;/span&gt;, and memory were all soldered directly onto the&amp;nbsp;motherboard.&lt;/p&gt;
&lt;p&gt;&lt;img alt="Solid state disk in the 2010 Macbook Air" src="https://ngjunsiang.github.io/laymansguide/issue136_03.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;The solid state disk in the 2010 Macbook Air&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/Teardown/MacBook+Air+11-Inch+Late+2010+Teardown/3745"&gt;iFixit&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;&lt;img alt="Wifi network card on a 2010 Macbook Air" src="https://ngjunsiang.github.io/laymansguide/issue136_04.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;The wifi network card on the 2010 Macbook Air&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/Teardown/MacBook+Air+11-Inch+Late+2010+Teardown/3745"&gt;iFixit&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;&lt;img alt="CPU and GPU on a 2010 Macbook Air, exposed without cooler" src="https://ngjunsiang.github.io/laymansguide/issue136_05.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;The &lt;span class="caps"&gt;CPU&lt;/span&gt; (left) and &lt;span class="caps"&gt;GPU&lt;/span&gt; (right) on the 2010 Macbook Air&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/Teardown/MacBook+Air+11-Inch+Late+2010+Teardown/3745"&gt;iFixit&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;&lt;img alt="Mainboard of a 2010 Macbook Air" src="https://ngjunsiang.github.io/laymansguide/issue136_06.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;Another view. &lt;span class="caps"&gt;CPU&lt;/span&gt; (red), &lt;span class="caps"&gt;GPU&lt;/span&gt; (orange), and memory (yellow) are directly soldered onto the mainboard&lt;br /&gt;Where is the chipset? I don’t know; the Macbook Air does not seem to use the same chipset as Intel-powered desktops&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/Teardown/MacBook+Air+11-Inch+Late+2010+Teardown/3745"&gt;iFixit&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;h2&gt;The slim laptop in 2018: also Macbook&amp;nbsp;Air&lt;/h2&gt;
&lt;p&gt;By 2018, while the outside of the Macbook Air still looks much the same, the insides are rather&amp;nbsp;different:&lt;/p&gt;
&lt;p&gt;&lt;img alt="Mainboard of a 2018 Macbook Air (top view)" src="https://ngjunsiang.github.io/laymansguide/issue136_07.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;&lt;span class="caps"&gt;CPU&lt;/span&gt; (red) and solid state disk (yellow) are directly soldered onto the mainboard&lt;br /&gt;Where’s the chipset? Notice that the &lt;span class="caps"&gt;CPU&lt;/span&gt; seems to have &lt;/em&gt;2 chips&lt;em&gt; on it? They are the &lt;span class="caps"&gt;CPU&lt;/span&gt; and chipset; two chips in one &lt;span class="caps"&gt;CPU&lt;/span&gt; package!&lt;br /&gt;The next image shows the reverse side. Other chips are ignored here, see the iFixit article for full identification&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/Teardown/MacBook+Air+13-Inch+Retina+2018+Teardown/115201"&gt;iFixit&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;&lt;img alt="Mainboard of a 2018 Macbook Air (bottom view)" src="https://ngjunsiang.github.io/laymansguide/issue136_08.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;Memory (red) and wifi network chip (orange) are &lt;/em&gt;also&lt;em&gt; directly soldered onto the mainboard&lt;br /&gt;This laptop only had integrated graphics; Intel had upped its integrated graphics performance sufficiently by this point&lt;br /&gt;Other chips are ignored here, see the iFixit article for full identification&lt;br /&gt;Source: &lt;a href="https://www.ifixit.com/Teardown/MacBook+Air+13-Inch+Retina+2018+Teardown/115201"&gt;iFixit&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;Components which in the 2010 Air were on separate cards are now all soldered directly to the mainboard! On the one hand, this saves space, which can be used for other features, or just for larger batteries. It also reduces the cost of manufacturing; connectors are costly to engineer and manufacture. On the other hand, it means upgradeability goes out the&amp;nbsp;window.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Issue summary:&lt;/strong&gt; Slim laptops have been undergoing a gradual transition: more and more of their chips are no longer available as a replaceable card, but instead soldered directly to the mainboard. Since 2017/2018, most slim laptops pretty much have &lt;span class="caps"&gt;CPU&lt;/span&gt;, memory, storage, and network chips all soldered directly to the&amp;nbsp;mainboard.&lt;/p&gt;
&lt;p&gt;Sorry about the image dump, I figured it would still be more convenient than having to click-through to see the images&amp;nbsp;:)&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S10] Issue 137: The M1 Macbook&amp;nbsp;Air&lt;/p&gt;
&lt;p&gt;The M1 goes even further than the 2018 Macbook Air, in one pretty significant way. Next issue, we compare how the Intel and M1 Macbooks Air&amp;nbsp;differ!&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;</content><category term="Season 11"></category></entry><entry><title>Issue 135: Part 2 – Unifying the CPU and MCH (post-2008)</title><link href="https://ngjunsiang.github.io/laymansguide/issue135.html" rel="alternate"></link><published>2021-08-28T08:00:00+08:00</published><updated>2021-08-28T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-08-28:/laymansguide/issue135.html</id><summary type="html">&lt;p&gt;A modern &lt;span class="caps"&gt;CPU&lt;/span&gt; is manufactured through a process called photolithography, by which the &lt;span class="caps"&gt;CPU&lt;/span&gt; components are etched onto the silicon substrate by successive layers of chemicals, masking, and laser exposure. When the &lt;span class="caps"&gt;CPU&lt;/span&gt; components could be made small enough, the &lt;span class="caps"&gt;MCH&lt;/span&gt; and &lt;span class="caps"&gt;CPU&lt;/span&gt; were designed onto the same chip, and this is the design used by the Intel Core i7&amp;nbsp;(1st-gen).&lt;/p&gt;</summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; Light takes 0.3 ns to travel 10 cm, approximately the distance by wire between the &lt;span class="caps"&gt;CPU&lt;/span&gt; and the &lt;span class="caps"&gt;MCH&lt;/span&gt;. This potentially causes operations between the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;MCH&lt;/span&gt; to slow down by one cycle, at frequencies above 3 GHz. One way the Intel Core i-series resolves this conundrum is to move the &lt;span class="caps"&gt;MCH&lt;/span&gt; &lt;em&gt;into&lt;/em&gt; the &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;&lt;img alt="Chipset diagram of ATX systems for Intel Core (i-Series)" src="https://ngjunsiang.github.io/laymansguide/issue134_02.gif" /&gt;&lt;br /&gt;
&lt;em&gt;An Intel Core i-series &lt;span class="caps"&gt;ATX&lt;/span&gt; system chipset diagram.&lt;br /&gt;The &lt;span class="caps"&gt;MCH&lt;/span&gt; is merged into the &lt;span class="caps"&gt;CPU&lt;/span&gt;, but still a discrete unit.&lt;br /&gt;&lt;span class="caps"&gt;DDR&lt;/span&gt; refers to computer memory, while &lt;span class="caps"&gt;GDDR&lt;/span&gt; refers to graphics card memory (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue123.html"&gt;Issue123&lt;/a&gt;))&lt;br /&gt;Source: &lt;a href="https://arstechnica.com/gadgets/2009/09/intel-launches-all-new-pc-architecture-with-core-i5i7-cpus/"&gt;Ars&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;Time to close up some open plot points from last&amp;nbsp;issue:&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;The number of pins on 1st-gen Core i7 is almost triple that of the Pentium 4; what are all those pins&amp;nbsp;for?&lt;/li&gt;
&lt;li&gt;The &lt;span class="caps"&gt;MCH&lt;/span&gt; has been moved into the &lt;span class="caps"&gt;CPU&lt;/span&gt; to improve latencies, but how is it possible to make it small enough to do&amp;nbsp;that?&lt;/li&gt;
&lt;li&gt;Are there any&amp;nbsp;disadvantages?&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;I’ll answer the second question first. It’s quite simple&amp;nbsp;really.&lt;/p&gt;
&lt;p&gt;You see, for circuit components, size doesn’t always benefit performance. A large transistor does essentially the same thing as a smaller transistor. So making them smaller is advantageous really; you can fit more into a single&amp;nbsp;chip!&lt;/p&gt;
&lt;h2&gt;Making a modern &lt;span class="caps"&gt;CPU&lt;/span&gt;&lt;/h2&gt;
&lt;p&gt;Modern CPUs are manufactured through a process called &lt;strong&gt;photolithography&lt;/strong&gt;—literally it means “etching with light” (Greek; &lt;em&gt;photo-&lt;/em&gt; “light” + &lt;em&gt;litho-&lt;/em&gt; “stone” + &lt;em&gt;-graphie&lt;/em&gt; “to draw”). By layering chemicals over the silicon base, putting a mask over them, and exposing them to light, a series of chemical reactions are induced to create the circuit pattern on the &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;Multiple CPUs are created on a single die this way, then individually cut and processed, in multiple steps spanning several months&lt;sup id="fnref:1"&gt;&lt;a class="footnote-ref" href="#fn:1"&gt;1&lt;/a&gt;&lt;/sup&gt;. The precision and fineness of the etching laser determine how small we can create components on this substrate. As the manufacturing process improves, semiconductor manufacturing companies are able to create CPUs that can cram more and more transistors into each square mm (or inch) of silicon&amp;nbsp;die.&lt;/p&gt;
&lt;p&gt;Besides being able to cram more transistors into the same space, it turns out that smaller components also use much less power! So we not only get performance gains, we get power efficiency gains as well—two birds with one&amp;nbsp;stone.&lt;/p&gt;
&lt;p&gt;&lt;img alt="CPU diagram of the Intel Core i7 (1st-gen)" src="https://ngjunsiang.github.io/laymansguide/issue135_01.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;&lt;span class="caps"&gt;CPU&lt;/span&gt; diagram of the Intel Core i7 (1st-gen)&lt;br /&gt;The memory controller, misc. &lt;span class="caps"&gt;IO&lt;/span&gt;, and &lt;span class="caps"&gt;QPI&lt;/span&gt; areas perform the role that the &lt;span class="caps"&gt;MCH&lt;/span&gt; used to take up&lt;br /&gt;Source: &lt;a href="https://www.anandtech.com/print/2658/"&gt;AnandTech&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;h2&gt;Moving&amp;nbsp;in&lt;/h2&gt;
&lt;p&gt;Over multiple generations of process improvements, the &lt;span class="caps"&gt;MCH&lt;/span&gt; and the &lt;span class="caps"&gt;CPU&lt;/span&gt; could finally be made small enough that they could both reasonably fit into the same die. There are, of course, &lt;em&gt;implications&lt;/em&gt;.&lt;/p&gt;
&lt;p&gt;Previously, the &lt;span class="caps"&gt;CPU&lt;/span&gt; only needed pins to communicate with the &lt;span class="caps"&gt;MCH&lt;/span&gt;. Now, the combined chip needs more pins than before to communicate with the computer memory, graphics processing unit (&lt;span class="caps"&gt;GPU&lt;/span&gt;), and &lt;span class="caps"&gt;PCH&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;So that answers the first question of what the additional pins are&amp;nbsp;for.&lt;/p&gt;
&lt;h2&gt;Working as one&amp;nbsp;unit&lt;/h2&gt;
&lt;p&gt;Which leaves the third question: besides latency improvements, are there any other&amp;nbsp;advantages?&lt;/p&gt;
&lt;p&gt;Mainboard manufacturers save on the cost of the &lt;span class="caps"&gt;MCH&lt;/span&gt; chipset, &lt;a href="https://www.anandtech.com/show/2824"&gt;which works out to about $40&lt;/a&gt;. Pretty significant when a mid-range mainboard costs&amp;nbsp;$80–$160.&lt;/p&gt;
&lt;p&gt;With the &lt;span class="caps"&gt;MCH&lt;/span&gt; and its requisite wires gone, the mainboard can be shrunk further; motherboards gradually shrank from &lt;span class="caps"&gt;ATX&lt;/span&gt; and microATX form factor sizes, to smaller form factors, such as &lt;span class="caps"&gt;ITX&lt;/span&gt; and the current popular &lt;span class="caps"&gt;NUC&lt;/span&gt; form&amp;nbsp;factors.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Mainboard form&amp;nbsp;factors&lt;/strong&gt;&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;ATX&lt;/span&gt;: 30×24cm (12×9.6&amp;nbsp;in)&lt;/li&gt;
&lt;li&gt;microATX: 24×24cm (9.6×9.6&amp;nbsp;in)&lt;/li&gt;
&lt;li&gt;&lt;span class="caps"&gt;ITX&lt;/span&gt;: 17×17cm (7×7&amp;nbsp;in)&lt;/li&gt;
&lt;li&gt;&lt;span class="caps"&gt;NUC&lt;/span&gt;: 10×10cm (4×4&amp;nbsp;in)&lt;/li&gt;
&lt;/ul&gt;
&lt;p&gt;And the disadvantages &amp;#8230; well, none on the consumer side actually. It seems to be positive all&amp;nbsp;around!&lt;/p&gt;
&lt;p&gt;Well actually, complexity rears its ugly head in power-saving&amp;nbsp;features.&lt;/p&gt;
&lt;p&gt;Previously, when the computer is in standby (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue115.html"&gt;Issue 115&lt;/a&gt;)), the &lt;span class="caps"&gt;CPU&lt;/span&gt; could be safely shut down (i.e. cut power to &lt;span class="caps"&gt;CPU&lt;/span&gt;), leaving only the &lt;span class="caps"&gt;MCH&lt;/span&gt; minimally powered so the computer memory retains its&amp;nbsp;information.&lt;/p&gt;
&lt;p&gt;With the &lt;span class="caps"&gt;MCH&lt;/span&gt; and the &lt;span class="caps"&gt;CPU&lt;/span&gt; now sharing the same chip, they have to be put in separate power zones so that the &lt;span class="caps"&gt;MCH&lt;/span&gt; portion remains powered while in standby, while the &lt;span class="caps"&gt;CPU&lt;/span&gt; can be shut down safely, making the chip more complicated than its&amp;nbsp;predecessors.&lt;/p&gt;
&lt;p&gt;But that is of little concern for us&amp;nbsp;layfolks.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Issue summary:&lt;/strong&gt; A modern &lt;span class="caps"&gt;CPU&lt;/span&gt; is manufactured through a process called photolithography, by which the &lt;span class="caps"&gt;CPU&lt;/span&gt; components are etched onto the silicon substrate by successive layers of chemicals, masking, and laser exposure. When the &lt;span class="caps"&gt;CPU&lt;/span&gt; components could be made small enough, the &lt;span class="caps"&gt;MCH&lt;/span&gt; and &lt;span class="caps"&gt;CPU&lt;/span&gt; were designed onto the same chip, and this is the design used by the Intel Core i7&amp;nbsp;(1st-gen).&lt;/p&gt;
&lt;p&gt;This is where the story stops with Intel for this season; their current-gen Core series still uses much the same chipset diagram, and a similar basic architecture, so there’s little new info of relevance for me to add&amp;nbsp;here.&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S10] Issue 136: The mobile workstation –&amp;nbsp;laptops&lt;/p&gt;
&lt;p&gt;To continue the story towards the Apple M1, it’s time to switch our lens to the mobile world: tablets, smartphones, and things smaller than a laptop. How are these things designed? What are their CPUs like? We’ll examine the evolution of the iconic Macbook Air, from 2010 to 2020 (warning:&amp;nbsp;image-heavy!)&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;
&lt;div class="footnote"&gt;
&lt;hr /&gt;
&lt;ol&gt;
&lt;li id="fn:1"&gt;
&lt;p&gt;See &lt;a href="https://www.washingtonpost.com/technology/2021/07/07/making-semiconductors-is-hard/"&gt;Three months, 700 steps: Why it takes so long to produce a computer chip (WashPo)&lt;/a&gt; for a more comprehensive description of the process&amp;#160;&lt;a class="footnote-backref" href="#fnref:1" title="Jump back to footnote 1 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;/ol&gt;
&lt;/div&gt;</content><category term="Season 11"></category></entry><entry><title>Issue 134: Part 1 – the Intel Core i-series launches!</title><link href="https://ngjunsiang.github.io/laymansguide/issue134.html" rel="alternate"></link><published>2021-08-21T08:00:00+08:00</published><updated>2021-08-21T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-08-21:/laymansguide/issue134.html</id><summary type="html">&lt;p&gt;Light takes 0.3 ns to travel 10 cm, approximately the distance by wire between the &lt;span class="caps"&gt;CPU&lt;/span&gt; and the &lt;span class="caps"&gt;MCH&lt;/span&gt;. This potentially causes operations between the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;MCH&lt;/span&gt; to slow down by one cycle, at frequencies above 3 GHz. One way the Intel Core i-series resolves this conundrum is to move the memory controller &lt;em&gt;into&lt;/em&gt; the &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;/p&gt;</summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; The &lt;span class="caps"&gt;ATX&lt;/span&gt; form factor also brought with it a new breed of computers with more specialised chipsets: the memory controller hub (&lt;span class="caps"&gt;MCH&lt;/span&gt;) and peripheral controller hub (&lt;span class="caps"&gt;PCH&lt;/span&gt;). The &lt;span class="caps"&gt;MCH&lt;/span&gt; specialises in high-throughput requirements, such as computer memory and graphics. The &lt;span class="caps"&gt;PCH&lt;/span&gt; specialises in lower-throughput&amp;nbsp;needs.&lt;/p&gt;
&lt;p&gt;Last issue, we looked at the &lt;span class="caps"&gt;ATX&lt;/span&gt; form factor by Intel, which replaced the &lt;span class="caps"&gt;AT&lt;/span&gt; form factor by &lt;span class="caps"&gt;IBM&lt;/span&gt;. While the &lt;span class="caps"&gt;AT&lt;/span&gt; could get by with a smattering of chips, which worked fine for mostly text-only computers, the &lt;span class="caps"&gt;ATX&lt;/span&gt; has much higher throughput requirements. To help the &lt;span class="caps"&gt;CPU&lt;/span&gt; focus on serving the user’s applications, two chipsets—the memory controller hub (&lt;span class="caps"&gt;MCH&lt;/span&gt;) and peripheral controller hub (&lt;span class="caps"&gt;PCH&lt;/span&gt;), take charge of managing the data throughput. The &lt;span class="caps"&gt;MCH&lt;/span&gt; manages data between &lt;span class="caps"&gt;CPU&lt;/span&gt;, computer memory, the graphics processor unit (&lt;span class="caps"&gt;GPU&lt;/span&gt;), and the &lt;span class="caps"&gt;PCH&lt;/span&gt;, while the &lt;span class="caps"&gt;PCH&lt;/span&gt; manages data between the peripherals (audio, storage, network, &lt;span class="caps"&gt;USB&lt;/span&gt;, &amp;#8230;) and the &lt;span class="caps"&gt;MCH&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;&lt;img alt="Chipset diagram of ATX systems, up to early Intel Core (i-Series)" src="https://ngjunsiang.github.io/laymansguide/issue134_01.gif" /&gt;&lt;br /&gt;
&lt;em&gt;An Intel pre-Core i-series &lt;span class="caps"&gt;ATX&lt;/span&gt; system chipset diagram.&lt;br /&gt;The &lt;span class="caps"&gt;MCH&lt;/span&gt; and &lt;span class="caps"&gt;PCH&lt;/span&gt; (labelled &lt;span class="caps"&gt;ICH&lt;/span&gt; here for unimportant reasons) support the &lt;span class="caps"&gt;CPU&lt;/span&gt; in its data operations&lt;br /&gt;&lt;span class="caps"&gt;DDR&lt;/span&gt; refers to computer memory, while &lt;span class="caps"&gt;GDDR&lt;/span&gt; refers to graphics card memory (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue123.html"&gt;Issue123&lt;/a&gt;))&lt;br /&gt;Source: &lt;a href="https://arstechnica.com/gadgets/2009/09/intel-launches-all-new-pc-architecture-with-core-i5i7-cpus/"&gt;Ars&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;There are terms for each of the connections between chips, which I won’t get into because it largely won’t concern us until we have to design performant&amp;nbsp;systems.&lt;/p&gt;
&lt;h2&gt;The evolution of Intel &lt;span class="caps"&gt;ATX&lt;/span&gt;&lt;/h2&gt;
&lt;p&gt;The technical geeks are probably fuming at this point because &lt;span class="caps"&gt;ATX&lt;/span&gt; is a motherboard standard, while I’m talking about the evolution of processors which have little to do with the motherboards, at least not directly &amp;#8230; but that’s of little importance at this point. Because we first need to talk about &lt;span class="caps"&gt;CPU&lt;/span&gt;&amp;nbsp;pins.&lt;/p&gt;
&lt;p&gt;From &lt;a href="https://ngjunsiang.github.io/laymansguide/issue131.html"&gt;Issue 131&lt;/a&gt;), I gave a simple model of the limitations of data&amp;nbsp;transfer:&lt;/p&gt;
&lt;blockquote&gt;
&lt;p&gt;There is a max frequency they can operate at, and a limit to the number of wires they can be connected to (throughput = no. of wires ×&amp;nbsp;frequency)&lt;/p&gt;
&lt;/blockquote&gt;
&lt;p&gt;The number of pins on processors have been steadily increasing up to this point, and so have the frequencies of processors. The Pentium 4 was succeeded by the Pentium D, then the Pentium Dual Core, then the Core 2. This Core processor preceded the Core i3/i5/i7 processors we know today; I’ll refer to this family of processors as the pre-i Core (rather than the more technical &lt;span class="caps"&gt;LGA775&lt;/span&gt;&amp;nbsp;series).&lt;/p&gt;
&lt;p&gt;Pentium 4: 478 pins&lt;br /&gt;
Core, Core 2 (pre-i Core): 775 pins&lt;br /&gt;
Core (i7, first-gen): &lt;strong&gt;1155&amp;nbsp;pins&lt;/strong&gt;&lt;/p&gt;
&lt;p&gt;Yup, the number of pins have &lt;em&gt;almost tripled&lt;/em&gt; since the Pentium 4! Remember that more pins does not make the &lt;span class="caps"&gt;CPU&lt;/span&gt; &lt;em&gt;itself&lt;/em&gt; calculate faster, it just helps it to &lt;em&gt;transfer data&lt;/em&gt;&amp;nbsp;faster.&lt;/p&gt;
&lt;p&gt;What are all those pins for, if there is the &lt;span class="caps"&gt;MCH&lt;/span&gt; to manage data&amp;nbsp;flow?&lt;/p&gt;
&lt;p&gt;Let’s talk about the limitations of the pre-i Core&amp;nbsp;setup.&lt;/p&gt;
&lt;h2&gt;Communication at a&amp;nbsp;distance&lt;/h2&gt;
&lt;p&gt;Wait … don’t electrical signals travel at &lt;em&gt;speeds near the speed of light&lt;/em&gt;?&lt;sup id="fnref:1"&gt;&lt;a class="footnote-ref" href="#fn:1"&gt;1&lt;/a&gt;&lt;/sup&gt; How would disappearing the &lt;span class="caps"&gt;MCH&lt;/span&gt; improve&amp;nbsp;latency?&lt;/p&gt;
&lt;p&gt;Consider some&amp;nbsp;numbers:&lt;/p&gt;
&lt;p&gt;The typical distance between the &lt;span class="caps"&gt;CPU&lt;/span&gt; and the &lt;span class="caps"&gt;MCH&lt;/span&gt; is about 5 cm (2 in). Since the wires between them are not straight, let’s approximately double that to 10 cm (4 in). Light would take 0.3 ns to travel that distance. Which is roughly one clock cycle on a 3 GHz processor—at 3 billion cycles per second, each cycle takes a third of a billionth of a second!&lt;sup id="fnref2:1"&gt;&lt;a class="footnote-ref" href="#fn:1"&gt;1&lt;/a&gt;&lt;/sup&gt;&lt;/p&gt;
&lt;p&gt;Remember that everything in a computer needs to happen like clockwork: for data to sync up, when the &lt;span class="caps"&gt;CPU&lt;/span&gt; sets a bit to one, the other party has to detect the bit signal before the clock cycle ends. If not, it will have to wait for the next clock cycle, causing the operation to slow down and take two clock cycles instead of&amp;nbsp;one.&lt;/p&gt;
&lt;p&gt;It’s like when you don’t manage to post the mail by 5pm, the postman has emptied the mailbox, and now you have to wait for 5pm the next day for your mail to be picked up&amp;nbsp;instead.&lt;/p&gt;
&lt;h2&gt;It’s all about throughput &amp;#8230; but also&amp;nbsp;latency&lt;/h2&gt;
&lt;p&gt;If light is taking one clock cycle to get out of the &lt;span class="caps"&gt;CPU&lt;/span&gt;, you have a problem. Raise the frequency higher than 3GHz, and you can cause a one-cycle lag just waiting for data to come in from the &lt;span class="caps"&gt;MCH&lt;/span&gt;, and to go out again to the &lt;span class="caps"&gt;MCH&lt;/span&gt;. That would counter-intuitively &lt;em&gt;slow down&lt;/em&gt; the &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;Solution: move the &lt;span class="caps"&gt;MCH&lt;/span&gt; into the &lt;span class="caps"&gt;CPU&lt;/span&gt;!&lt;/p&gt;
&lt;p&gt;&lt;img alt="Chipset diagram of ATX systems for Intel Core (i-Series)" src="https://ngjunsiang.github.io/laymansguide/issue134_02.gif" /&gt;&lt;br /&gt;
&lt;em&gt;An Intel Core i-series &lt;span class="caps"&gt;ATX&lt;/span&gt; system chipset diagram.&lt;br /&gt;The &lt;span class="caps"&gt;MCH&lt;/span&gt; is merged into the &lt;span class="caps"&gt;CPU&lt;/span&gt;, but still a discrete unit.&lt;br /&gt;&lt;span class="caps"&gt;DDR&lt;/span&gt; refers to computer memory, while &lt;span class="caps"&gt;GDDR&lt;/span&gt; refers to graphics card memory (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue123.html"&gt;Issue123&lt;/a&gt;))&lt;br /&gt;Source: &lt;a href="https://arstechnica.com/gadgets/2009/09/intel-launches-all-new-pc-architecture-with-core-i5i7-cpus/"&gt;Ars&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;h2&gt;Squeezing more tenants into the&amp;nbsp;building&lt;/h2&gt;
&lt;p&gt;Wait &amp;#8230; you can just do&amp;nbsp;that?&lt;/p&gt;
&lt;p&gt;I will need many more issues to lay out the mechanics of this, so I won’t—I think it’s way beyond the scope of a layman’s guide at that point!—but let’s see what I can come up with in the next&amp;nbsp;issue.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Issue summary:&lt;/strong&gt; Light takes 0.3 ns to travel 10 cm, approximately the distance by wire between the &lt;span class="caps"&gt;CPU&lt;/span&gt; and the &lt;span class="caps"&gt;MCH&lt;/span&gt;. This potentially causes operations between the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;MCH&lt;/span&gt; to slow down by one cycle, at frequencies above 3 GHz. One way the Intel Core i-series resolves this conundrum is to move the memory controller &lt;em&gt;into&lt;/em&gt; the &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;This is what I spent years reading and thinking about to explain, and I finally get to lay it out in text. Incredibly excited to get to the next few&amp;nbsp;issues!&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S10] Issue 135: Part 2 – Unifying the &lt;span class="caps"&gt;CPU&lt;/span&gt; and &lt;span class="caps"&gt;MCH&lt;/span&gt;&amp;nbsp;(post-2008)&lt;/p&gt;
&lt;p&gt;Next issue: how the &lt;span class="caps"&gt;ATX&lt;/span&gt; form factor evolved to eliminate the &lt;span class="caps"&gt;MCH&lt;/span&gt;. Sorry to end on a&amp;nbsp;cliffhanger!&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;
&lt;div class="footnote"&gt;
&lt;hr /&gt;
&lt;ol&gt;
&lt;li id="fn:1"&gt;
&lt;p&gt;I want to just make a note here that while I believe my choice of analogy is justified, the numbers are wildly off: &lt;a href="https://www.realworldtech.com/nehalem/3/"&gt;RealWorldTech here puts the 1st-gen Core at approx 30 ns&lt;/a&gt;, for technical reasons that will take at least half a season to unpack (definitely not layman content!). But he also notes that latency for remote memory (i.e. memory not on the &lt;span class="caps"&gt;CPU&lt;/span&gt;, but on the motherboard) is “roughly 30 ns slower than local [memory]” (i.e. memory residing directly on the &lt;span class="caps"&gt;CPU&lt;/span&gt;). So the remote-vs-local latency gap is real and significant!&amp;#160;&lt;a class="footnote-backref" href="#fnref:1" title="Jump back to footnote 1 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;a class="footnote-backref" href="#fnref2:1" title="Jump back to footnote 1 in the text"&gt;&amp;#8617;&lt;/a&gt;&lt;/p&gt;
&lt;/li&gt;
&lt;/ol&gt;
&lt;/div&gt;</content><category term="Season 11"></category></entry><entry><title>Issue 133: the ATX form factor (post-1995)</title><link href="https://ngjunsiang.github.io/laymansguide/issue133.html" rel="alternate"></link><published>2021-08-14T08:00:00+08:00</published><updated>2021-08-14T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-08-14:/laymansguide/issue133.html</id><summary type="html">&lt;p&gt;The &lt;span class="caps"&gt;ATX&lt;/span&gt; form factor also brought with it a new breed of computers with more specialised chipsets: the memory controller hub (&lt;span class="caps"&gt;MCH&lt;/span&gt;) and peripheral controller hub (&lt;span class="caps"&gt;PCH&lt;/span&gt;). The &lt;span class="caps"&gt;MCH&lt;/span&gt; coordinates high-throughput components, such as computer memory and graphics. The &lt;span class="caps"&gt;PCH&lt;/span&gt; specialises in lower-throughput&amp;nbsp;needs.&lt;/p&gt;</summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; Chipsets served as go-betweens in the &lt;span class="caps"&gt;AT&lt;/span&gt; form factor by &lt;span class="caps"&gt;IBM&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;In 1993, Intel launched its Pentium line of processors; barely two years later, in 1995, Intel launched the &lt;span class="caps"&gt;ATX&lt;/span&gt; form factor. This was the beginning of Intel’s dominance in the desktop space, and they could well afford to dictate most of the standards for this form&amp;nbsp;factor.&lt;/p&gt;
&lt;h2&gt;Chipset&amp;nbsp;diagram&lt;/h2&gt;
&lt;p&gt;Mainboards at this point were complicated enough that as part of the marketing, tech publications had taken to staring at diagrams of how the chips were connected. These diagrams are called &lt;strong&gt;chipset diagrams&lt;/strong&gt;.&lt;/p&gt;
&lt;p&gt;This is the chipset diagram of a typical mainboard for the Pentium&amp;nbsp;4:&lt;/p&gt;
&lt;p&gt;&lt;img alt="Chipset diagram of a mainboard for the Pentium 4" src="https://ngjunsiang.github.io/laymansguide/issue133_02.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;I tried to find a chipset diagram that used human terms instead of acronyms.&lt;br /&gt;This is the best I could do. Annotations my own.&lt;br /&gt;Source: &lt;a href="https://www.hexus.net/tech/reviews/mainboard/635-sis655fx-dual-channel-p4-chipset/?page=2"&gt;Hexus&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;The &lt;strong&gt;memory controller hub&lt;/strong&gt; (&lt;span class="caps"&gt;MCH&lt;/span&gt;) now takes on a much bigger role; it is managing data transfer between the &lt;span class="caps"&gt;CPU&lt;/span&gt;, graphics card, computer memory, &lt;em&gt;and&lt;/em&gt; the &lt;span class="caps"&gt;PCH&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;The &lt;strong&gt;peripheral controller hub&lt;/strong&gt; (&lt;span class="caps"&gt;PCH&lt;/span&gt;), while managing connections to many more devices, actually has less work to do; these are all low-throughput devices that don’t send much data to the &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;/p&gt;
&lt;h2&gt;&lt;span class="caps"&gt;ATX&lt;/span&gt;&amp;nbsp;mainboard&lt;/h2&gt;
&lt;p&gt;And this is where the components are found on the&amp;nbsp;motherboard:&lt;/p&gt;
&lt;p&gt;&lt;img alt="A mainboard for the Pentium 4" src="https://ngjunsiang.github.io/laymansguide/issue133_01.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;A motherboard for the Pentium 4, with key components outlined.&lt;br /&gt;Annotations are my&amp;nbsp;own.&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;The &lt;span class="caps"&gt;CPU&lt;/span&gt; clearly draws the most power and produces the most heat here. But notice now that the &lt;span class="caps"&gt;MCH&lt;/span&gt; is no longer bare; it now produces so much heat (&lt;a href="https://hexus.net/tech/news/mainboard/132515-der8auer-examines-amd-x570-chipset-power-consumption/"&gt;4–10 W&lt;/a&gt;) that it needs to be passively cooled with a heatsink (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue129.html"&gt;Issue 129&lt;/a&gt;)). the &lt;span class="caps"&gt;PCH&lt;/span&gt;, on the other hand, is still chill enough to get by bare naked (4 W or&amp;nbsp;less).&lt;/p&gt;
&lt;p&gt;3D graphics at this point is a rapidly growing industry, especially for videogames. Graphics cards needed much more throughput to the &lt;span class="caps"&gt;CPU&lt;/span&gt; and memory, so the &lt;span class="caps"&gt;MCH&lt;/span&gt; grew to fit into this role as the mediator between these throughput-hungry&amp;nbsp;components&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Issue summary:&lt;/strong&gt; The &lt;span class="caps"&gt;ATX&lt;/span&gt; form factor also brought with it a new breed of computers with more specialised chipsets: the memory controller hub (&lt;span class="caps"&gt;MCH&lt;/span&gt;) and peripheral controller hub (&lt;span class="caps"&gt;PCH&lt;/span&gt;). The &lt;span class="caps"&gt;MCH&lt;/span&gt; coordinates high-throughput components, such as computer memory and graphics. The &lt;span class="caps"&gt;PCH&lt;/span&gt; specialises in lower-throughput&amp;nbsp;needs.&lt;/p&gt;
&lt;p&gt;Much as I try to avoid using acronyms, here they are really just easier to&amp;nbsp;read.&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S10] Issue 134: Part 1 – the Intel Core i-series&amp;nbsp;launches!&lt;/p&gt;
&lt;p&gt;I don’t know if you noticed, but there seem to be fewer chips here than on the &lt;span class="caps"&gt;AT&lt;/span&gt; board. That’s misleading though; the components that were on the &lt;span class="caps"&gt;AT&lt;/span&gt; board are also on the &lt;span class="caps"&gt;ATX&lt;/span&gt; board, but greatly shrunk. Some of the functionality that used to require multiple chips on &lt;span class="caps"&gt;AT&lt;/span&gt; have been replaced by a single chip in &lt;span class="caps"&gt;ATX&lt;/span&gt;, hence the appearance of simplicity. In reality, the &lt;span class="caps"&gt;ATX&lt;/span&gt; mainboard is more&amp;nbsp;complex!&lt;/p&gt;
&lt;p&gt;Next issue, onward with the&amp;nbsp;integration!&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;</content><category term="Season 11"></category></entry><entry><title>Issue 132: the AT form factor (pre-1995)</title><link href="https://ngjunsiang.github.io/laymansguide/issue132.html" rel="alternate"></link><published>2021-08-07T08:00:00+08:00</published><updated>2021-08-07T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-08-07:/laymansguide/issue132.html</id><summary type="html">&lt;p&gt;Chipsets served as go-betweens in the &lt;span class="caps"&gt;AT&lt;/span&gt; form factor by &lt;span class="caps"&gt;IBM&lt;/span&gt;.&lt;/p&gt;</summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; CPUs have limited throughput, since there is a max frequency they can operate at, and a limit to the number of wires they can be connected to (throughput = no. of wires × frequency). Later designs of early computers increased the capability of computers by delegating more work to secondary&amp;nbsp;chips.&lt;/p&gt;
&lt;p&gt;When computers began hitting the mainstream market, they were designed to be able to use interchangeable parts so as to reduce cost and inventory. To support this effort, manufacturers came up with standards for how to lay out computer components on a mainboard; the different patterns came to be known as &lt;strong&gt;form factors&lt;/strong&gt;.&lt;/p&gt;
&lt;p&gt;The &lt;span class="caps"&gt;AT&lt;/span&gt; form factor, by &lt;span class="caps"&gt;IBM&lt;/span&gt;, is one of the early ones. An &lt;span class="caps"&gt;AT&lt;/span&gt; motherboard looks something like&amp;nbsp;this:&lt;/p&gt;
&lt;h2&gt;The &lt;span class="caps"&gt;AT&lt;/span&gt;&amp;nbsp;mainboard&lt;/h2&gt;
&lt;p&gt;&lt;img alt="An AT motherboard" src="https://ngjunsiang.github.io/laymansguide/issue132_01.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;An &lt;span class="caps"&gt;AT&lt;/span&gt; motherboard, with key components outlined.&lt;br /&gt;Annotations are my own.&lt;br /&gt;Original: &lt;a href="https://en.wikipedia.org/wiki/Skylake_(microarchitecture)"&gt;Wikipedia&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;Graphics cards, usually added as an expansion card, communicated with the &lt;span class="caps"&gt;CPU&lt;/span&gt; (under the heatsink) through a chipset, while the &lt;span class="caps"&gt;CPU&lt;/span&gt; communicated with memory through another&amp;nbsp;chipset.&lt;/p&gt;
&lt;p&gt;At this point, graphics were still barely powerful enough to run 3D graphics (this was before Windows 95!), and the chipsets mainly served as go-betweens between memory, expansion slots (called buses), and the &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;/p&gt;
&lt;p&gt;After 1995, this would&amp;nbsp;change.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Issue summary:&lt;/strong&gt; Chipsets served as go-betweens in the &lt;span class="caps"&gt;AT&lt;/span&gt; form factor by &lt;span class="caps"&gt;IBM&lt;/span&gt;.&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S10] Issue 133: the &lt;span class="caps"&gt;ATX&lt;/span&gt; form factor&amp;nbsp;(post-1995)&lt;/p&gt;
&lt;p&gt;Short issue here, just to introduce the idea of chipsets! You can see the chips on the &lt;span class="caps"&gt;AT&lt;/span&gt; board look very similar. On the &lt;span class="caps"&gt;ATX&lt;/span&gt; form factor, they will begin to differentiate and&amp;nbsp;specialise.&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;</content><category term="Season 11"></category></entry><entry><title>Issue 131: What do early CPUs and startup founders have in common?</title><link href="https://ngjunsiang.github.io/laymansguide/issue131.html" rel="alternate"></link><published>2021-07-31T08:00:00+08:00</published><updated>2021-07-31T08:00:00+08:00</updated><author><name>J S Ng</name></author><id>tag:ngjunsiang.github.io,2021-07-31:/laymansguide/issue131.html</id><summary type="html">&lt;p&gt;CPUs have limited throughput, since there is a max frequency they can operate at, and a limit to the number of wires they can be connected to (throughput = no. of wires × frequency). Later designs of early computers increased the capability of computers by delegating more work to secondary&amp;nbsp;chips.&lt;/p&gt;</summary><content type="html">&lt;p&gt;&lt;strong&gt;Previously:&lt;/strong&gt; &lt;span class="caps"&gt;AC&lt;/span&gt; power from the wall uses electric current that alternates directions, while &lt;span class="caps"&gt;DC&lt;/span&gt; power from batteries uses electric current that flows in one direction only. All electronics are &lt;span class="caps"&gt;DC&lt;/span&gt;-only, and require an &lt;span class="caps"&gt;AC&lt;/span&gt;-&lt;span class="caps"&gt;DC&lt;/span&gt; adapter to be powered from the wall. The &lt;span class="caps"&gt;AC&lt;/span&gt;-&lt;span class="caps"&gt;DC&lt;/span&gt; conversion produces a significant amount of heat; &lt;span class="caps"&gt;AC&lt;/span&gt;-&lt;span class="caps"&gt;DC&lt;/span&gt; adapters are usually external unless the device has sufficient space or cooling capacity for&amp;nbsp;it.&lt;/p&gt;
&lt;p&gt;This season, let’s open up that computer case and see what’s inside. Where does everything fit, and how does all that information get around? More importantly, how are computers able to cover such a large range of sizes, from towering desktops to tiny&amp;nbsp;smartphones?&lt;/p&gt;
&lt;h2&gt;What a computer wants, what a computer&amp;nbsp;needs&lt;/h2&gt;
&lt;p&gt;The common model of a computer is that it … computes. It calculates. It takes in numbers, and spits out more&amp;nbsp;numbers.&lt;/p&gt;
&lt;p&gt;That’s not quite&amp;nbsp;right.&lt;/p&gt;
&lt;p&gt;While a computer does carry out compute operations, these are far outnumbered by load/store operations (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue058.html"&gt;Issue 58&lt;/a&gt;)). Why so much loading and storing of&amp;nbsp;data?&lt;/p&gt;
&lt;h2&gt;Moving&amp;nbsp;data&lt;/h2&gt;
&lt;p&gt;The &lt;span class="caps"&gt;CPU&lt;/span&gt; itself has precious little storage (&amp;lt;20 &lt;span class="caps"&gt;MB&lt;/span&gt; of cache storage); it is only a wee little chip! Most of the data in a computer is stored in a hard drive or solid state drive; let’s just call them storage drives for&amp;nbsp;now.&lt;/p&gt;
&lt;p&gt;So CPUs have to read data from a storage drive. This is a slow operation, because storage drives are slow; writing to storage drives is even slower than reading from&amp;nbsp;them.&lt;/p&gt;
&lt;p&gt;In the meantime, the &lt;span class="caps"&gt;CPU&lt;/span&gt; needs a place to dump working data; this is computer memory (2–&lt;span class="caps"&gt;32GB&lt;/span&gt;). Memory is slower than the &lt;span class="caps"&gt;CPU&lt;/span&gt;’s cache, but much faster than a storage&amp;nbsp;drive.&lt;/p&gt;
&lt;p&gt;That’s 3 places to stash data so far: storage drives, &lt;span class="caps"&gt;CPU&lt;/span&gt; cache, and computer memory. You with me so&amp;nbsp;far?&lt;/p&gt;
&lt;h2&gt;Pipelines&lt;/h2&gt;
&lt;p&gt;The next place that often requires lots of data is the graphics card (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue123.html"&gt;Issue 123&lt;/a&gt;)). For you to play a video game, the computer has&amp;nbsp;to:&lt;/p&gt;
&lt;ol&gt;
&lt;li&gt;Load game data from the storage&amp;nbsp;disk,&lt;/li&gt;
&lt;li&gt;Store most of it in memory while it’s doing some number crunching in its&amp;nbsp;cache,&lt;/li&gt;
&lt;li&gt;Get the crunched numbers to the graphics card for rendering graphics (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue122.html"&gt;Issue 122&lt;/a&gt;)),&lt;/li&gt;
&lt;li&gt;Load more data from memory while crunching more numbers, and passing them to the graphics&amp;nbsp;card.&lt;/li&gt;
&lt;/ol&gt;
&lt;p&gt;This involves far more loading and storing than computation. And there are limitations to how quickly data can be&amp;nbsp;transferred.&lt;/p&gt;
&lt;h2&gt;Throughput&lt;/h2&gt;
&lt;p&gt;How does data get transferred? Through very fine wires usually. One side (e.g. the &lt;span class="caps"&gt;CPU&lt;/span&gt;) applies a voltage to the wire, the other side (e.g. memory) checks the voltage on the wire. No applied voltage = 0, applied voltage =&amp;nbsp;1.&lt;/p&gt;
&lt;p&gt;How does the &lt;span class="caps"&gt;CPU&lt;/span&gt; know when to apply the voltage, and the memory know when to check it? These operations are synchronised through cycles, like a highly coordinated factory. A &lt;span class="caps"&gt;CPU&lt;/span&gt; operates on a frequency of up to billions of cycles per second, each cycle potentially transferring one bit of data (&lt;a href="https://ngjunsiang.github.io/laymansguide/issue040.html"&gt;Issue 40&lt;/a&gt;)) if there are no&amp;nbsp;delays.&lt;/p&gt;
&lt;p&gt;Typically, the transfer rate is somewhat slower; how do we transfer more data per second? By adding more wires! With two wires, we can transfer two bits per cycle; four wires = four bits per second, eight wires = 8 bits per second … at some point, we run into a different problem. The &lt;span class="caps"&gt;CPU&lt;/span&gt; is a small chip, and there is only so much surface area for us to connect wires&amp;nbsp;to.&lt;/p&gt;
&lt;p&gt;&lt;img alt="An Intel Skylake CPU, showing the pins underneath" src="https://ngjunsiang.github.io/laymansguide/issue131_01.jpg" /&gt;&lt;br /&gt;
&lt;em&gt;An Intel Skylake desktop &lt;span class="caps"&gt;CPU&lt;/span&gt;.&lt;br /&gt;Each gold contact on the under-surface connects to a pin on the motherboard when the &lt;span class="caps"&gt;CPU&lt;/span&gt; is seated properly in its socket&lt;br /&gt;Source: &lt;a href="https://en.wikipedia.org/wiki/Skylake_(microarchitecture)"&gt;Wikipedia&lt;/a&gt;&lt;/em&gt;    &lt;/p&gt;
&lt;p&gt;Well, that just&amp;nbsp;sucks.&lt;/p&gt;
&lt;h2&gt;The limits of one&amp;nbsp;chip&lt;/h2&gt;
&lt;p&gt;Come to think of it, humans are much the same; we only have two hands and two legs, there are limits to how fast we can do things, and limits to how long we can stay awake working. We mostly get around these limitations by learning to&amp;nbsp;delegate.&lt;/p&gt;
&lt;p&gt;In the same way, computer designs evolved to delegate more work to secondary chips, leaving the &lt;span class="caps"&gt;CPU&lt;/span&gt; to focus on computation. We’ll explore the gradual evolution of these architectures, so you can better appreciate the elegance of the Apple M1’s design&amp;nbsp;;)&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Issue summary:&lt;/strong&gt; CPUs have limited throughput, since there is a max frequency they can operate at, and a limit to the number of wires they can be connected to (throughput = no. of wires × frequency). Later designs of early computers increased the capability of computers by delegating more work to secondary&amp;nbsp;chips.&lt;/p&gt;
&lt;p&gt;The more I learned about computer architecture, the more I see parallels to startups and organisational culture in general. I was really looking at ways of organising information flows, and observing how the computational limitations of different parts influence the design of the whole chip! This is a constant work in progress, which is why we keep seeing new &lt;span class="caps"&gt;CPU&lt;/span&gt; designs emerge each&amp;nbsp;year.&lt;/p&gt;
&lt;h2&gt;What I’ll be covering&amp;nbsp;next&lt;/h2&gt;
&lt;p&gt;&lt;strong&gt;Next issue:&lt;/strong&gt; [&lt;span class="caps"&gt;LMG&lt;/span&gt; S10] Issue 132: the &lt;span class="caps"&gt;AT&lt;/span&gt; form factor&amp;nbsp;(pre-1995)&lt;/p&gt;
&lt;p&gt;Let’s start from—nah, I wont go all the way back to the beginning, just to the point where computer architecture was already recognisable in its early modern form. Next issue, a big welcome for the &lt;span class="caps"&gt;AT&lt;/span&gt; form&amp;nbsp;factor!&lt;/p&gt;
&lt;p&gt;&lt;strong&gt;Sometime in the future:&lt;/strong&gt; What&amp;nbsp;is:&lt;/p&gt;
&lt;ul&gt;
&lt;li&gt;&lt;span class="caps"&gt;XSS&lt;/span&gt;? [Issue&amp;nbsp;8]&lt;/li&gt;
&lt;li&gt;a good reason developers write code and give it away for free online? [Issue&amp;nbsp;21]&lt;/li&gt;
&lt;li&gt;OpenType? And what are fonts anyway? [Issue&amp;nbsp;42]&lt;/li&gt;
&lt;/ul&gt;</content><category term="Season 11"></category><category term="cache"></category></entry></feed>